CC2430 Datasheet, PDF (97/212 Pages) Texas Instruments – A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee-TM

CC2430
Peripherals : DMA Controller
DMAREQ (0xD7) – DMA Channel Start Request and Status
Bit
Name
7:5 -
4
DMAREQ4
3
DMAREQ3
2
DMAREQ2
1
DMAREQ1
0
DMAREQ0
Reset
000
0
R/W
R0
R/W1
H0
0
R/W1
H0
0
R/W1
H0
0
R/W1
H0
0
R/W1
H0
Description
Not used
DMA transfer request, channel 4
When set to 1 activate the DMA channel (has the same
effect as a single trigger event.). Only by setting the armed
bit to 0 in the DMAARM register, can the channel be
stopped if already started.
This bit is cleared when the DMA channel is granted
access.
DMA transfer request, channel 3
When set to 1 activate the DMA channel (has the same
effect as a single trigger event.). Only by setting the armed
bit to 0 in the DMAARM register, can the channel be
stopped if already started.
This bit is cleared when the DMA channel is granted
access.
DMA transfer request, channel 2
When set to 1 activate the DMA channel (has the same
effect as a single trigger event.). Only by setting the armed
bit to 0 in the DMAARM register, can the channel be
stopped if already started.
This bit is cleared when the DMA channel is granted
access.
DMA transfer request, channel 1
When set to 1 activate the DMA channel (has the same
effect as a single trigger event.). Only by setting the armed
bit to 0 in the DMAARM register, can the channel be
stopped if already started.
This bit is cleared when the DMA channel is granted
access.
DMA transfer request, channel 0
When set to 1 activate the DMA channel (has the same
effect as a single trigger event.). Only by setting the armed
bit to 0 in the DMAARM register, can the channel be
stopped if already started.
This bit is cleared when the DMA channel is granted
access.
DMA0CFGH (0xD5) – DMA Channel 0 Configuration Address High Byte
Bit Name
7:0 DMA0CFG[15:8]
Reset R/W
0x00 R/W
Description
The DMA channel 0 configuration address, high order
DMA0CFGL (0xD4) – DMA Channel 0 Configuration Address Low Byte
Bit Name
7:0 DMA0CFG[7:0]
Reset R/W
0x00 R/W
Description
The DMA channel 0 configuration address, low order
DMA1CFGH (0xD3) – DMA Channel 1-4 Configuration Address High Byte
Bit Name
7:0 DMA1CFG[15:8]
Reset R/W
0x00 R/W
Description
The DMA channel 1-4 configuration address, high order
CC2430 Data Sheet (rev. 2.1) SWRS036F
Page 97 of 211