CC2430 Datasheet, PDF (199/212 Pages) Texas Instruments – A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee-TM

IOCFG1 (0xDF50)
Bit Name
7
-
6
OE_CCA
5
IO_CCA_POL
4:0 IO_CCA_SEL
IOCFG2 (0xDF51)
Bit Name
7
-
6
OE_SFD
5
IO_SFD_POL
4:0 IO_SFD_SEL
IOCFG3 (0xDF52)
Bit Name
7:6 -
5:4 HSSD_SRC
3
OE_FIFOP
2
IO_FIFOP_POL
1
OE_FIFO
0
IO_FIFO_POL
RXFIFOCNT (0xDF53)
Bit Name
7:0 RXFIFOCNT[7:0]
Radio : Radio Registers
CC2430
Reset
0
0
0
00000
R/W
R0
R/W
R/W
R/W
Description
Reserved, read as 0.
CCA is output on P1.7 when this bit is 1
Polarity of the IO_CCA signal. This bit is xor’ed with the
internal CCA signal.
Multiplexer setting for the CCA signal. Must be 0x00 in
order to output the CCA status.
Reset
0
0
0
00000
R/W
R0
R/W
R/W
R/W
Description
Reserved, read as 0.
SFD is output on P1.6 when this bit is 1
Polarity of the IO_SFD signal. This bit is xor’ed with the
internal SFD signal.
Multiplexer setting for the SFD signal. Must be 0x00 in order
to output the SFD status
Reset
00
00
0
0
0
0
R/W
R0
R/W
R/W
R/W
R/W
R/W
Description
Reserved, read as 0.
Configures the HSSD interface. Only the first 4 settings
(compared to CC2420) are used.
00 : Off
01 : Output AGC status (gain setting/peak detector
status/accumulator value)
10 : Output ADC I and Q values
11 : Output I/Q after digital down mix and channel filtering
FIFOP is output on P1.5 when this bit is 1.
Polarity of the IO_FIFOP signal. This bit is xor’ed with the
internal FIFOP signal
FIFO is output on P1.4 when this bit is 1
Polarity of the IO_FIFO signal. This bit is xor’ed with the
internal FIFO signal
Reset
0x00
R/W
R
Description
Number of bytes in the RX FIFO
CC2430 Data Sheet (rev. 2.1) SWRS036F
Page 199 of 211