CC2430 Datasheet, PDF (105/212 Pages) Texas Instruments – A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee-TM

Peripherals : 16-bit timer, Timer1
CC2430
T1CC0
T1CCn
0000h
0 - Set output on com pare
1 - Clear output on com pare
2 - Toggle output on com pare
3 - Set output on com pare-up,
clear on com pare-down
4 - Clear output on com pare-up,
set on compare-down
5 - Clear when T1CC0, set when T1CCn
6 - Set when T1CC0, clear when T1CCn
T1CCn T1CC0 T1CCn
T1CCn T1CC0 T1CCn
Figure 25: Output modes, timer up/down mode
13.6.9 Timer 1 Interrupts
There is one interrupt vector assigned to the
timer. An interrupt request is generated when
one of the following timer events occur:
• Counter reaches terminal count value
(overflow, or turns around zero.
• Input capture event.
• Output compare event
The register bits T1CTL.OVFIF,
T1CTL.CH0IF,
T1CTL.CH1IF,
and
T1CTL.CH2IF contains the interrupt flags for
the terminal count value event, and the three
13.6.10 Timer 1 DMA Triggers
There are three DMA triggers associated with
Timer 1. These are DMA triggers T1_CH0,
T1_CH1 and T1_CH2 which are generated on
timer compare events as follows:
channel compare/capture events, respectively.
An interrupt request is only generated when
the corresponding interrupt mask bit is set
together witjh IEN1.T1EN. The interrupt mask
bits are T1CCTL0.IM, T1CCTL1.IM,
T1CCTL2.IM and TIMIF.OVFIM. If there are
other pending interrupts, the corresponding
interrupt flag must be cleared by software
before a new interrupt request is generated.
Also, enabling an interrupt mask bit will
generate a new interrupt request if the
corresponding interrupt flag is set.
• T1_CH0 – channel 0 compare
• T1_CH1 – channel 1 compare
• T1_CH2 – channel 2 compare
CC2430 Data Sheet (rev. 2.1) SWRS036F
Page 105 of 211