CC2430 Datasheet, PDF (33/212 Pages) Texas Instruments – A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee-TM

8051 CPU : Memory
CC2430
11.2.2 CPU Memory Space
This section describes the details of each CPU
memory space.
XDATA memory space. The XDATA memory
map is given in Figure 7. For devices with flash
size above 32 KB only 56 KB of the flash
memory is mapped into XDATA, address
range 0x0000-0xDEFF. For the 32 KB flash
size option, the 32 KB flash memory is
mapped to 0x0000-0x7FFF in XDATA.
Access to unimplemented areas in the
memory map gives an undefined result
(applies to F32 only).
For all device flash-options, the 8 KB SRAM is
mapped into address range 0xE000-0xFFFF.
The SFR registers are mapped into address
range 0xDF80-0xDFFF, and are also equal on
all flash options.
Another memory-mapped register area is the
RF register area which is mapped into the
address range 0xDF00-0xDF7F. These
registers are associated with the radio (see
sections 14 and 14.35) and are also equal on
all flash options.
The mapping of flash memory, SRAM and
registers to XDATA allows the DMA controller
and the CPU access to all the physical
memories in a single unified address space
(maximum of 56 KB flash, above reserved for
CODE). Note that the CODE banking scheme,
described in CODE memory space section, will
not affect the contents of the 24 KB above the
32KB lowest memory area, thus XDATA
mapps into the Flash as shown in Figure 7.
One of the ramifications of this mapping is that
the first address of usable SRAM starts at
address 0xE000 instead of 0x0000, and
therefore compilers/assemblers must take this
into consideration.
In low-power modes PM2-3 the upper 4 KB of
SRAM, i.e. the memory locations in XDATA
address range 0xF000-0xFFFF, will retain their
contents. There are some locations in this area
that are excepted from retention and thus does
not keep its data in these power modes. Refer
to section 13.1 on page 65 for a detailed
description of power modes and SRAM data
retention.
CODE memory space. The CODE memory
space uses either a unified or a non-unified
memory mapping (see section 11.2.1 on page
30) to the physical memories as shown in
Figure 8 and Figure 9. The unified mapping of
the CODE memory space is similar to the
XDATA mapping. Note that some SFR
registers internal to the CPU can not be
accessed in the unified CODE memory space
(see section 11.2.3, SFR registers, on page
34).
With flash memory sizes above 32 KB, only 56
KB of flash memory is mapped to CODE
memory space at a time when unified mapping
is used. The upper 24 KB follows the banking
scheme described below and shown in Figure
9. This is similar to the XDATA memory space
exept for the upper 24 KB that can change
content. Using unified memory CODE data at
address above 0xDEFF will not contain flash
data.
The 8 KB SRAM is included in the unified
CODE address space to allow program
execution out of the SRAM.
Note: In order to use the unified memory
mapping within CODE memory space, the
SFR register bit MEMCTR.MUNIF must be 1.
For devices with flash memory size of 128 KB
(CC2430F128), a flash memory banking
scheme is used for the CODE memory space.
For the banking scheme the upper 32 KB area
of CODE memory space is mapped to one out
of the four 32 KB physical blocks (banks) of
flash memory. The lower 32 KB of CODE
space is always mapped to the lowest 32 KB
of the flash memory. The banking is controlled
through the flash bank select bit (FMAP.MAP)
and shown in the non-unified CODE memory
map in Figure 8. The flash bank select bits
reside in the SFR register bits FMAP.MAP, and
also in the SFR register bits MEMCTR.FMAP,
(see section 11.2.5 on page 40). The
FMAP.MAP bit and MEMCTR.FMAP bit are
transparent and updating one is reflected by
the other.
When banking and unified CODE memory
space are used, only the lower 24 KB in the
selected bank is available. This is shown in
Figure 9.
DATA memory space. The 8-bit address
range of DATA memory is mapped into the
upper 256 bytes of the 8 KB SRAM. This area
is also accessible through the unified CODE
and XDATA memory spaces at the address
range 0xFF00-0xFFFF.
SFR memory space. The 128 entry hardware
register area is accessed through this memory
space. The SFR registers are also accessible
through the XDATA address space at the
address range 0xDF80-0xDFFF. Some CPU-
CC2430 Data Sheet (rev. 2.1) SWRS036F
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