CC2430 Datasheet, PDF (130/212 Pages) Texas Instruments – A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee-TM

CC2430
Peripherals : ADC
where Vinn=0V). The maximum value is
reached when the input amplitude is equal
VREF, the selected voltage reference. For
differential configurations the difference
between two pin pairs are converted and this
differense can be negatively signed. For 12-bit
resolution the digital conversion result is 2047
when the analog input, Vconv, is equal to
VREF, and the conversion result is -2048
when the analog input is equal to –VREF.
1. Note that the conversion result always
resides in MSB section of combined ADCH
and ADCL registers.
When the ADCCON2.SCH bits are read, they
will indicate the channel above the channel
which the conversion result in ADCL and ADCH
apply to. E.g. reading the value 0x1 from
ADCCON2.SCH, means that the available
conversion result is from input AIN0.
The digital conversion result is available in
ADCH and ADCL when ADCCON1.EOC is set to
13.10.2.6 ADC Reference Voltage
The positive reference voltage for analog-to-
digital conversions is selectable as either an
internally generated 1.25V voltage, the
AVDD_SOC pin, an external voltage applied to
the AIN7 input pin or a differential voltage
applied to the AIN6-AIN7 inputs.
It is possible to select the reference voltage as
the input to the ADC in order to perform a
conversion of the reference voltage e.g. for
calibration purposes. Similarly, it is possible to
select the ground terminal GND as an input.
13.10.2.7 ADC Conversion Timing
The ADC should be run when on the 32MHz
system clock, which is divided by 8 to give a 4
MHz clock. Both the delta sigma modulator
and decimation filter expect 4 MHz clock for
their calculations. Using other frequencies will
affect the results, and conversion time. All data
presented within this data sheet are from
32MHz system clock usage.
The time required to perform a conversion
depends on the selected decimation rate.
When the decimation rate is set to for instance
128, the decimation filter uses exactly 128 of
the 4 MHz clock periods to calculate the result.
When a conversion is started, the input
multiplexer is allowed 16 4 MHz clock cycles to
settle in case the channel has been changed
since the previous conversion. The 16 clock
cycles settling time applies to all decimation
rates. Thus in general, the conversion time is
given by:
Tconv = (decimation rate + 16) x 0.25 µs.
13.10.2.8 ADC Interrupts
The ADC will generate an interrupt when an
extra conversion has completed. An interrupt
is not generated when a conversion from the
sequence is completed.
13.10.2.9 ADC DMA Triggers
The ADC will generate a DMA trigger every
time a conversion from the sequence has
completed. When an extra conversion
completes, no DMA trigger is generated.
There is one DMA trigger for each of the eight
channels defined by the first eight possible
settings for ADCCON2.SCH . The DMA trigger
is active when a new sample is ready from the
13.10.2.10 ADC Registers
This section describes the ADC registers.
ADCL (0xBA) – ADC Data Low
conversion for the channel. The DMA triggers
are named ADC_CHsd in Table 41 on page
94, where s is single ended channel and d is
differential channel.
In addition there is one DMA trigger,
ADC_CHALL, which is active when new data
is ready from any of the channels in the ADC
conversion sequence.
Bit Name
7:2 _ADC[5:0]
1:0 -
Reset R/W
0x00 R
00
R0
Description
Least significant part of ADC conversion result.
Not used. Always read as 0
CC2430 Data Sheet (rev. 2.1) SWRS036F
Page 130 of 211