CC2430 Datasheet, PDF (102/212 Pages) Texas Instruments – A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee-TM

CC2430
Peripherals : 16-bit timer, Timer1
when the counter reaches 0x0000 instead of
when a compare occurs.
Examples of output compare modes in various
timer modes are given in the following figures.
Edge-aligned: PWM output signals can be
generated using the timer modulo mode and
channels 1 and 2 in output compare mode 6 or
7 (defined by T1CCTLn.CMP bits, wher n is 1
or 2) as shown in Figure 23. The period of the
PWM signal is determined by the setting in
T1CC0 and the duty cycle is determined by
T1CCn, where n is the PWM channel 1 or 2.
The timer free-running mode may also be
used. In this case CLKCON.TICKSPD and the
prescaler divider value in T1CTL.DIV bits
set the period of the PWM signal. The polarity
of the PWM signal is determined by whether
output compare mode 6 or 7 is used.
PWM output signals can also be generated
using output compare modes 4 and 5 as
shown in Figure 23, or by using modulo mode
as shown in Figure 24. Using output compare
mode 4 and 5 is preferred for simple PWM.
Centre-aligned: PWM outputs can be
generated when the timer up/down mode is
selected. The channel output compare mode 4
or 5 (defined by T1CCTLn.CMP bits, wher n is
1 or 2) is selected depending on required
polarity of the PWM signal. The period of the
PWM signal is determined by T1CC0 and the
duty cycle for the channel output is determined
by T1CCn, where n is the PWM channel 1 or 2.
The centre-aligned PWM mode is required by
certain types of motor drive applications and
typically less noise is produced than the edge-
aligned PWM mode because the I/O pin
transitions are not lined up on the same clock
edge.
In some types of applications, a defined delay
or dead time is required between outputs.
Typically this is required for outputs driving an
H-bridge configuration to avoid uncontrolled
cross-conduction in one side of the H-bridge.
The delay or dead-time can be obtained in the
PWM outputs by using T1CCn as shown in the
following:
Assuming that channel 1 and channel 2 are
used to drive the outputs using timer up/down
mode and the channels use output compare
modes 4 and 5 respectively, then the timer
period (in Timer 1 clock periods) is:
T_P = T1CC0 x 2
and the dead time, i.e. the time when both
outputs are low, (in Timer 1 clock periods) is
given by:
T_D = T1CC1 – T1CC2
CC2430 Data Sheet (rev. 2.1) SWRS036F
Page 102 of 211