CC2430 Datasheet, PDF (34/212 Pages) Texas Instruments – A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee-TM

CC2430
8051 CPU : Memory
specific SFR registers reside inside the CPU
core and can only be accessed using the SFR
memory space and not through the duplicate
mapping into XDATA memory space. These
specific SFR registers are listed in section
11.2.3, SFR registers, on page 34.
11.2.3 Physical memory
RAM. The CC2430 contains static RAM. At
power-on the contents of RAM is undefined.
The RAM size is 8 KB in total. The upper 4 KB
of the RAM (XDATA memory locations
0xF000-0xFFFF) retains data in all power
modes (see exception below). The remaining
lower 4 KB (XDATA memory locations
0xE000-0xEFFF) will loose its contents in PM2
and PM3 and contains undefined data when
returning to PM0.
The memory locations 0xFD56-0xFEFF
(XDATA) consists of 426 bytes in RAM that
will not retain data when PM2/3 is entered.
Flash Memory. The on-chip flash memory
consists of 32768, 655536 or 131072 bytes.
The flash memory is primarily intended to hold
program code. The flash memory has the
following features:
• Flash page erase time: 20 ms
• Flash chip (mass) erase time: 200 ms
• Flash write time (4 bytes): 20 µs
• Data retention⁵:100 years
• Program/erase endurance: 1,000 cycles
The flash memory consists of the Flash Main
Pages (up to 64 times 2 KB) which is where
the CPU reads program code and data. The
flash memory also contains a Flash
Information Page (2 KB) which contains the
Flash Lock Bits. The Flash Information Page
and hence the Lock Bits is only accessed
through the Debug Interface, and must be
selected as source prior to access. The Flash
5 _{At room temperature}
Controller (see section 13.3) is used to write
and erase the contents of the flash main
memory.
When the CPU reads instructions from flash
memory, it fetches the next instruction through
a cache. The instruction cache is provided
mainly to reduce power consumption by
reducing the amount of time the flash memory
itself is accessed. The use of the instruction
cache may be disabled with the
MEMCTR.CACHDIS register bit, but doing so
will increase power consuption.
SFR Registers. The Special Function
Registers (SFRs) control several of the
features of the 8051 CPU core and/or
peripherals. Many of the 8051 core SFRs are
identical to the standard 8051 SFRs. However,
there are additional SFRs that control features
that are not available in the standard 8051.
The additional SFRs are used to interface with
the peripheral units and RF transceiver.
Table 24 shows the address to all SFRs in
CC2430. The 8051 internal SFRs are shown
with grey background, while the other SFRs
are the SFRs specific to CC2430.
Note: All internal SFRs (shown with grey
background in Table 24), can only be
accessed through SFR space as these
registers are not mapped into XDATA space.
Table 25 lists the additional SFRs that are not
standard 8051 peripheral SFRs or CPU-
internal SFRs. The additional SFRs are
described in the relevant sections for each
peripheral function.
CC2430 Data Sheet (rev. 2.1) SWRS036F
Page 34 of 211