CC2430 Datasheet, PDF (180/212 Pages) Texas Instruments – A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee-TM

CC2430
NMONIC OPCODE
DECZ
DECY
INCY
0xBF
0xBE
0xBD
INCMAXY
0xB0|M¹²
RANDXY
INT
0xBC
0xB9
WAITX
0xBB
WAIT W
0x80|W¹²
WEVENT
0xB8
LABEL
0xBA
RPT C
0xA0|N|C¹²
SKIP S,C 0x00|S|N|C¹²
Radio : CSMA/CA Strobe Processor
Table 47: CSMA/CA strobe processor instruction details
Function
Operation
Description
Decrement Z
Z := Z - 1
The Z register is decremented by 1. Original values of 0x00 will underflow to 0x0FF.
Decrement Y
Y := Y - 1
The Y register is decremented by 1. Original values of 0x00 will underflow to 0x0FF.
Increment Y
Y := Y + 1
The Y register is incremented by 1. An original value of 0x0FF will overflow to 0x00.
Increment Y !> M
Y := min(Y+1, M)
The Y register is incremented by 1 if the result is less than M otherwise Y register is
loaded with value M. An original value of Y equal 0x0FF will result in the value M.
Load random data into X
X[Y-1:0] := RNG_DOUT[Y-1:0],
X[7:Y] := 0
The [Y] LSB bits of X register are loaded with random value. Note that if two RANDXY
instructions are issued immediately after each other the same random value will be
used in both cases. If Y equals 0 or if Y is greater than 8, then 8 LSB bits are loaded.
Interrupt
IRQ_CSP_INT = 1
The interrupt IRQ_CSP_INT is asserted when this instruction is executed.
Wait for X MAC Timer
overflows
X := X-1 when MAC timer overflow true
PC := PC while number of MAC timer
compare true < X
PC := PC + 1 when number of MAC timer
compare true = X
Wait until MAC Timer overflows the numbers of times equal to register X. The contents
of register X is decremented each time a MAC Timer overflow is detected. Program
execution continues with the next instruction and the interrupt flag IRQ_CSP_WT is
asserted when the wait condition is true. If register X is zero when this instruction
starts executing, there is no wait.
Wait for W MAC Timer
overflows
PC := PC while number of MAC timer
compare true < W
PC := PC + 1 when number of MAC timer
compare true = W
Wait until MAC Timer overflows number of times equal to value W. If W=0 the
instruction will wait for 32 overflows. Program execution continues with the next
instruction and the interrupt flag IRQ_CSP_WT is asserted when the wait condition is
true.
Wait until MAC Timer compare
PC :=
PC :=
true
PC
PC
while MAC timer compare false
+ 1 when MAC timer compare
Wait MAC Timer value is greater than or equal to the compare value in T2CMP.
Program execution continues with the next instruction when the wait condition is true.
Set loop label
LABEL:= PC+1
Sets next instruction as start of loop. If the current instruction is the last instruction in
the instruction memory then the current PC is set as start of loop. Only one level of
loops is supported.
Conditional repeat
PC := LABEL when
(C xor N) true
PC := PC + 1 when
(C xor N) false or LABEL not set
If condition C is true then jump to instruction defined by last LABEL instruction, i.e.
jump to start of loop. If the condition is false or if a LABEL instruction has not been
executed, then execution will continue from next instruction. The condition C may be
negated by setting N=1 and is described in Table 48.
Conditional skip instruction
PC := PC + S + 1 when (C xor N) true
else
PC := PC + 1
If condition C is true then skip S instructions. The condition C may be negated (N=1)
and is described in Table 48 (note same conditions as RPT C instruction). Setting S=0,
will cause a wait at current instruction until (C xor N) = true
12 _{Refer to Table 46 for OPCODE}
CC2430 Data Sheet (rev. 2.1) SWRS036F
Page 180 of 211