CC2430 Datasheet, PDF (157/212 Pages) Texas Instruments – A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee-TM

CC2430
RFIM (0x91) – RF Interrupt Mask
Radio : FIFO access
Bit Name
7 _{IM_RREG_PD}
6 _{IM_TXDONE}
5 _{IM_FIFOP}
4 _{IM_SFD}
3 _{IM_CCA}
2 _{IM_CSP_WT}
1 _{IM_CSP_STOP}
0 _{IM_CSP_INT}
Reset R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Description
Voltage regulator for radio has been turned on
0 Interrupt disabled
1 Interrupt enabled
TX completed with packet sent. Also for acknowledge frames if RF
register IRQSRC.TXACK is 1
0 Interrupt disabled
1 Interrupt enabled
Number of bytes in RXFIFO is above threshold set by
IOCFG0.FIFOP_THR
0 Interrupt disabled
1 Interrupt enabled
Start of frame delimiter (SFD) has been detected
0 Interrupt disabled
1 Interrupt enabled
Clear channel assessment (CCA) indicates that channel is clear
0 Interrupt disabled
1 Interrupt enabled
CSMA-CA/strobe processor (CSP) wait condition is true
0 Interrupt disabled
1 Interrupt enabled
CSMA-CA/strobe processor (CSP) program execution stopped
0 Interrupt disabled
1 Interrupt enabled
CSMA-CA/strobe processor (CSP) INT instruction executed
0 Interrupt disabled
1 Interrupt enabled
14.5 FIFO access
The TXFIFO and RXFIFO may be accessed
through the SFR register RFD (0xD9).
Data is written to the TXFIFO when writing to
the RFD register. Data is read from the he
RXFIFO when the RFD register is read.
The RF register bits RFSTATUS.FIFO and
RFSTATUS.FIFOP provide information on the
data in the receive FIFO, as described in
section 14.6 on page 157. Note that the
RFD (0xD9) – RF Data
RFSTATUS.FIFO and RFSTATUS.FIFOP only
apply to the RXFIFO.
The TXFIFO may be flushed by issuing a
SFLUSHTX command strobe. Similarly, a
SFLUSHRX command strobe will flush the
receive FIFO.
The FIFO may contain 256 bytes (128 bytes
for RX and 128 bytes for TX).
Bit Name
7:0 RFD[7:0]
Reset R/W
0x00 R/W
Description
Data written to the register is written to the
TXFIFO. When reading this register, data from the
RXFIFO is read
14.6 DMA
It is possible, and in most cases
recommended, to use direct memory access
(DMA) to move data between memory and the
radio. The DMA controller is described in
section 13.5. Refer to this section for a
detailed description on how to setup and use
DMA transfers.
To support the DMA controller there is one
DMA trigger associated with the radio, this is
the RADIO DMA trigger (DMA trigger 19). The
RADIO DMA trigger is activated by two events.
The first event to cause a RADIO DMA trigger,
is when the first data is present in the RXFIFO,
i.e. when the RXFIFO goes from the empty
state to the non-empty state. The second
CC2430 Data Sheet (rev. 2.1) SWRS036F
Page 157 of 211