CC2430 Datasheet, PDF (78/212 Pages) Texas Instruments – A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee-TM

CC2430
Peripherals : I/O ports
• 21 digital input/output pins
• General purpose I/O or peripheral I/O
• Pull-up or pull-down capability on inputs
• External interrupt capability
The external interrupt capability is available on
all 21 I/O pins. Thus external devices may
generate interrupts if required. The external
interrupt feature can also be used to wake up
from sleep modes.
13.4.1 Unused I/O pins
Unused I/O pins should have a defined level
and not be left floating. One way to do this is to
leave the pin unconnected and configure the
pin as a general purpose I/O input with pull-up
resistor. This is also the state of all pins after
reset (note that only P2[2] has pull-up during
13.4.2 Low I/O Supply Voltage
In applications where the digital I/O power
supply voltage pin DVDD is below 2.6 V, the
register bit PICTL.PADSC should be set to 1
13.4.3 General Purpose I/O
When used as general purpose I/O, the pins
are organized as three 8-bit ports, ports 0-2,
denoted P0, P1 and P2. P0 and P1 are
complete 8-bit wide ports while P2 has only
five usable bits. All ports are both bit- and byte
addressable through the SFR registers P0, P1
and P2. Each port pin can individually be set to
operate as a general purpose I/O or as a
peripheral I/O.
The output drive strength is 4 mA on all
outputs, except for the two high-drive outputs,
P1_0 and P1_1, which each have 20 mA
output drive strength.
The registers PxSEL where x is the port
number 0-2 are used to configure each pin in a
port as either a general purpose I/O pin or as a
peripheral I/O signal. By default, after a reset,
all digital input/output pins are configured as
general-purpose input pins.
To change the direction of a port pin, at any
time, the registers PxDIR are used to set each
port pin to be either an input or an output.
Thus by setting the appropriate bit within
PxDIR, to 1 the corresponding pin becomes
an output.
reset). Alternatively the pin can be configured
as a general purpose I/O output. In both cases
the pin should not be connected directly to
VDD or GND in order to avoid excessive
power consumption.
in order to obtain output DC characteristics
specified in section 7.16.
When reading the port registers P0, P1 and
P2, the logic values on the input pins are
returned regardless of the pin configuration.
This does not apply during the execution of
read-modify-write instructions. The read-
modify-write instructions are: ANL, ORL, XRL,
JBC, CPL, INC, DEC, DJNZ and MOV, CLR or SETB.
Operating on a port registers the following is
true: When the destination is an individual bit
in a port register P0, P1 or P2 the value of the
register, not the value on the pin, is read,
modified, and written back to the port register.
When used as an input, the general purpose
I/O port pins can be configured to have a pull-
up, pull-down or tri-state mode of operation. By
default, after a reset, inputs are configured as
inputs with pull-up. To deselect the pull-up or
pull-down function on an input the appropriate
bit within the PxINP must be set to 1. The I/O
port pins P1_0 and P1_1 do not have pull-
up/pull-down capability.
In power modes PM2 and PM3 the I/O pins
retain the I/O mode and output value (if
applicable) that was set when PM2/3 was
entered.
13.4.4 General Purpose I/O Interrupts
General purpose I/O pins configured as inputs
can be used to generate interrupts. The
interrupts can be configured to trigger on either
a rising or falling edge of the external signal.
Each of the P0, P1 and P2 ports have
separate interrupt enable bits common for all
bits within the port located in the IEN1-2
registers as follows:
• IEN1.P0IE : P0 interrupt enable
• IEN2.P1IE : P1 interrupt enable
• IEN2.P2IE : P2 interrupt enable
In addition to these common interrupt enables,
the bits within each port have interrupt enables
located in I/O port SFR registers. Each bit
within P1 has an individual interrupt enable. In
P0 the low-order nibble and the high-order
CC2430 Data Sheet (rev. 2.1) SWRS036F
Page 78 of 211