CC2430 Datasheet, PDF (160/212 Pages) Texas Instruments – A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee-TM

Radio : General control and status
CC2430
Data^{STXcoOmsNtmroabned}
transmitted
over RF
SFD
Preamble
SFtDransmitted
SFD
Lengt
h
12 symbol periods
Automatically generated
preamble and SFD
MAC Protocol Data Unit (MPDU)
LasbtyMtteraPnTDsXUmuinttdeedroflor ^w
Data fetched
from TXFIFO
CRC
generated
Figure 37: SFD status activity example during transmit
14.10 General control and status
In receive mode, the RFIF.IRQ_FIFOP
interrupt flag and RF interrupt request can be
used to interrupt the CPU when a threshold
has been exceeded or a complete frame has
been received.
In receive mode, the RFSTATUS.FIFO bit can
be used to detect if there is data at all in the
receive FIFO.
The RFIF.IRQ_SFD interrupt flag can be used
to extract the timing information of transmitted
and received data frames. The
RFIF.IRQ_SFD bit will go high when a start of
frame delimiter has been completely detected /
transmitted.
For debug purposes, the RFSTATUS.SFD,
RFSTATUS.FIFO, RFSTATUS.FIFOP and
RFSTATUS.CCA bits can be output onto P1.7
– P1.4 I/O pins to monitor the status of these
signals as selected by the IOCFG0, IOCFG1
and IOCFG2 register.
The polarity of these signals given on the
debug outputs can also be controlled by the
IOCFG0-2 registers, if needed.
14.11 Demodulator, Symbol Synchronizer and Data Decision
The block diagram for the CC2430 demodulator
is shown in Figure 38. Channel filtering and
frequency offset compensation is performed
digitally. The signal level in the channel is
estimated to generate the RSSI level (see the
RSSI / Energy Detection section on page 168
for more information). Data filtering is also
included for enhanced performance.
With the ±40 ppm frequency accuracy
requirement from [1], a compliant receiver
must be able to compensate for up to 80 ppm
or 200 kHz. The CC2430 demodulator tolerates
up to 300 kHz offset without significant
degradation of the receiver performance.
Soft decision is used at the chip level, i.e. the
demodulator does not make a decision for
each chip, only for each received symbol. De-
spreading is performed using over-sampling
symbol correlators. Symbol synchronization is
achieved by a continuous start of frame
delimiter (SFD) search.
When an SFD is detected, data is written to
the RXFIFO and may be read out by the CPU
at a lower bit rate than the 250 kbps generated
by the receiver.
The CC2430 demodulator also handles symbol
rate errors in excess of 120 ppm without
performance degradation. Resynchronization
is performed continuously to adjust for error in
the incoming symbol rate.
The RF register MDMCTRL1H.CORR_THR
control bits should be written to 0x14 to set the
threshold for detecting IEEE 802.15.4 start of
frame delimiters.
CC2430 Data Sheet (rev. 2.1) SWRS036F
Page 160 of 211