CC2430 Datasheet, PDF (30/212 Pages) Texas Instruments – A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee-TM

8051 CPU : 8051 CPU Introduction
CC2430
11 8051 CPU
This section describes the 8051 CPU core,
with interrupts, memory and instruction set.
11.1 8051 CPU Introduction
The CC2430 includes an 8-bit CPU core which
is an enhanced version of the industry
standard 8051 core.
The enhanced 8051 core uses the standard
8051 instruction set. Instructions execute
faster than the standard 8051 due to the
following:
• One clock per instruction cycle is used as
opposed to 12 clocks per instruction cycle
in the standard 8051.
• Wasted bus states are eliminated.
Since an instruction cycle is aligned with
memory fetch when possible, most of the
single byte instructions are performed in a
single clock cycle. In addition to the speed
improvement, the enhanced 8051 core also
includes architectural enhancements:
11.2 Memory
The 8051 CPU architecture has four different
memory spaces. The 8051 has separate
memory spaces for program memory and data
memory. The 8051 memory spaces are the
following (see section 11.2.1 and 11.2.2 for
details):
CODE. A read-only memory space for
program memory. This memory space
addresses 64 KB.
DATA. A read/write data memory space,
which can be directly or indirectly, accessed by
a single cycle CPU instruction, thus allowing
fast access. This memory space addresses
256 bytes. The lower 128 bytes of the DATA
memory space can be addressed either
directly or indirectly, the upper 128 bytes only
indirectly.
XDATA. A read/write data memory space
access to which usually requires 4-5 CPU
instruction cycles, thus giving slow access.
This memory space addresses 64 KB. Access
to XDATA memory is also slower in hardware
11.2.1 Memory Map
This section gives an overview of the memory
map.
The memory map differs from the standard
8051 memory map in two important aspects,
as described below.
• A second data pointer.
• Extended 18-source interrupt unit
The 8051 core is object code compatible with
the industry standard 8051 microcontroller.
That is, object code compiled with an industry
standard 8051 compiler or assembler executes
on the 8051 core and is functionally
equivalent. However, because the 8051 core
uses a different instruction timing than many
other 8051 variants, existing code with timing
loops may require modification. Also because
the peripheral units such as timers and serial
ports differ from those on a other 8051 cores,
code which includes instructions using the
peripheral units SFRs will not work correctly.
than DATA access as the CODE and XDATA
memory spaces share a common bus on the
CPU core and instruction pre-fetch from CODE
can thus not be performed in parallel with
XDATA accesses.
SFR. A read/write register memory space
which can be directly accessed by a single
CPU instruction. This memory space consists
of 128 bytes. For SFR registers whose
address is divisible by eight, each bit is also
individually addressable.
The four different memory spaces are distinct
in the 8051 architecture, but are partly
overlapping in the CC2430 to ease DMA
transfers and hardware debugger operation.
How the different memory spaces are mapped
onto the three physical memories (flash
program memory, 8 KB SRAM and memory-
mapped registers) is described in sections
11.2.1 and 11.2.2.
First, in order to allow the DMA controller
access to all physical memory and thus allow
DMA transfers between the different 8051
memory spaces, parts of SFR and CODE
memory space are mapped into the XDATA
memory space.
CC2430 Data Sheet (rev. 2.1) SWRS036F
Page 30 of 211