CC2430 Datasheet, PDF (72/212 Pages) Texas Instruments – A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee-TM

CC2430
Peripherals : Flash Controller
The Flash Controller handles writing and
erasing the embedded flash memory. The
embedded flash memory consists of 64 pages
of 2048 bytes each (CC2430F128).
The flash controller has the following features:
• 32-bit word programmable
• Page erase
• Lock bits for write-protection and code
security
• Flash page erase timing 20 ms
• Flash chip erase timing 200 ms
• Flash write timing (4 bytes) 20 µs
• Auto power-down during low-frequency
CPU clock read access
13.3.1 Flash Memory Organization
The flash memory is divided into 64 flash
pages consisting of 2 KB each (all versions
have 2 KB pages, but the number of pages
differs and here 128 KB is referred). A flash
page is the smallest erasable unit in the
memory, while a 32 bit word is the smallest
writable unit that may be addressed through
the flash controller.
When performing write operations, the flash
memory is word-addressable using a 15-bit
address written to the address registers
FADDRH:FADDRL.
When performing page erase operations, the
flash memory page to be erased is addressed
through the register bits FADDRH[6:1].
Note the difference in addressing the flash
memory; when accessed by the CPU to read
code or data, the flash memory is byte-
addressable. When accessed by the Flash
Controller, the flash memory is word-
addressable, where a word consists of 32 bits.
The next sections describe the procedures for
flash write and flash page erase in detail.
13.3.2 Flash Write
Data is written to the flash memory by using a
program command initiated by writing the
Flash Control register, FCTL. Flash write
operations can program any number of words
in the flash memory, single words or block of
words in sequence starting at start address
(set by FADDRH:FADDRL). Each location may
be programmed twice before the next erase
must take place, meanaing that a bit in a word
can change from 1-1 or 1-0 but not 0-1 (writing
a 0 to 1 will be ignored). This can be utilized by
writing to different parts of the word with
masking without having to do a page erase
before writing. After a page erase or chip
erase (through debug interface), the erased
bits are set to 1.
A write operation is performed using one out of
two methods;
• Through DMA transfer
• Through CPU SFR access.
The DMA transfer method is the preferred way
to write to the flash memory.
A write operation is initiated by writing a 1 to
FCTL.WRITE. The start address for writing the
32-bit word is given by FADDRH:FADDRL.
During each single write operation
FCTL.SWBSY is set high. During a write
operation, the byte written to the FWDATA
register is forwarded to the flash memory. The
flash memory is 32-bit word-programmable,
meaning data is written as 32-bit words. The
first byte written to FWDATA is the LSB of the
32-bit word. The actual writing to flash memory
takes place each time four bytes have been
written to FWDATA, meaning that all Flash
writes must be 4 bytes aligned.
The CPU will not be able to access the flash,
e.g. to read program code, while a flash write
operation is in progress. Therefore the
program code executing the flash write must
be executed from RAM, meaning that the
program code must reside in the area 0xE000
to 0xFEFF in Unified CODE memory space.
When a flash write operation is executed from
RAM, the CPU continues to execute code from
the next instruction after initiation of the flash
write operation (FCTL.WRITE=1).
The FCTL.SWBSY bit must be 0 before
accessing the flash after a flash write,
otherwise an access violation occurs. This also
means that FCTL.SWBSY must be 0 before
program execution can continue from a
location in flash memory.
CC2430 Data Sheet (rev. 2.1) SWRS036F
Page 72 of 211