CC2430 Datasheet, PDF (111/212 Pages) Texas Instruments – A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee-TM

CC2430
Peripherals : MAC Timer (Timer2)
the timer is to be compared is set by the
T2CNF.CMSEL bit.
request is also generated if the interrupt mask
T2PEROF2.CMPIM is set to 1.
When a timer compare occurs the interrupt
flag T2CNF.CMPIF is set to 1. An interrupt
13.7.1.6
Capture Input
The MAC timer has a timer capture function
which captures at the time when the start of
frame delimiter (SFD) status in the radio goes
high. Refer to sections 14.6 and 14.9 starting
on page 157 for a description of the SFD.
When the capture event occurs the current
timer value will be captured into the capture
register. The capture value can be read from
the registers T2CAPHPH:T2CAPLPL. The
value of the overflow count is also captured
(see section 13.7.1.7) at the time of the
capture event and can be read from the
registers T2PEROF2:T2PEROF1:T2PEROF0.
13.7.1.7
Overflow count
At each timer overflow, the 20-bit overflow
counter is incremented by 1. The overflow
counter value is read through the SFR
registers T2OF2:T2OF1:T2OF0. Note that the
register contents in T2OF2:T2OF1 is latched
when T2OF0 is read, meaning that T2OF0
must always be read first.
Overflow count update: The overflow count
value may be updated by writing to the
registers T2OF2:T2OF1:T2OF0 when the
timer is in the IDLE or RUN state.
Note that the last data written to registers
T2OF1:T2OF0 is latched when T2OF2 is
written, meaning that T2OF2 must always be
written last.
13.7.1.8
Overflow count compare
A compare value may be set for the overflow
counter. The compare value is set by writing to
T2PEROF2:T2PEROF1:T2PEROF0. When
the overflow count value is equal or greater
than the set compare value an overflow
compare event occurs. If the overflow compare
interrupt mask bit T2PEROF2.OFCMPIM is 1,
an interrupt request is generated. The interrupt
flag bit T2CNF.OFCMPIF is set to 1 regardless
of the interrupt mask value. It should be noted
that if a capture event occurs when the
T2PEROF2 is written to the three most
significant bits will not be updated. In order to
address this one should either write twice to
this register while interrupts are disabled, or
read back and verify that written data was set.
13.7.2 Interrupts
The Timer has three individually maskable
interrupt sources. These are the following:
• Timer overflow
• Timer compare
• Overflow count compare
The interrupt flags are given in the T2CNF
registers. The interrupt flag bits are set only by
hardware and may be cleared only by writing
to the SFR register.
13.7.3 DMA Triggers
Timer 2 can generate two DMA triggers –
T2_COMP and T2_OVFL which are activated
as follows:
Each interrupt source may be masked by the
mask bits in the T2PEROF2 register. An
interrupt is generated when the corresponding
mask bit is set, otherwise the interrupt will not
be generated. The interrupt flag bit is set,
however disregarding the state of the interrupt
mask bit.
• T2_COMP: Timer 2 compare event
• T2_OVFL: Timer 2 overflow event
13.7.4 Timer start/stop synchronization
This section describes the synchronized timer
start and stop.
CC2430 Data Sheet (rev. 2.1) SWRS036F
Page 111 of 211