CC2430 Datasheet, PDF (96/212 Pages) Texas Instruments – A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee-TM

Byte Bit
Offset
7
2
Name
M8
7
1:0 PRIORITY[1:0]
CC2430
Peripherals : DMA Controller
Description
Mode of 8^th bit for VLEN transfer length; only applicable when WORDSIZE=0.
0 : Use all 8 bits for transfer count
1 : Use 7 LSB for transfer count
The DMA channel priority:
00 : Low, CPU has priority.
01 : Guaranteed, DMA at least every second try.
10 : High, DMA has priority
11 : Highest, DMA has priority. Reserved for DMA port access.
13.5.8 DMA registers
This section describes the SFR registers associated with the DMA Controller
DMAARM (0xD6) – DMA Channel Arm
Bit
Name
7
ABORT
Reset
0
R/W
R0/W
6:5 -
4
DMAARM4
3
DMAARM3
2
DMAARM2
1
DMAARM1
0
DMAARM0
00
R/W
0
R/W1
0
R/W1
0
R/W1
0
R/W1
0
R/W1
Description
DMA abort. This bit is used to stop ongoing DMA transfers.
Writing a 1 to this bit will abort all channels which are selected
by setting the corresponding DMAARM bit to 1
0 : Normal operation
1 : Abort all selected channels
Not used
DMA arm channel 4
This bit must be set in order for any DMA transfers to occur on
the channel. For non-repetitive transfer modes, the bit is
automatically cleared upon completion.
DMA arm channel 3
This bit must be set in order for any DMA transfers to occur on
the channel. For non-repetitive transfer modes, the bit is
automatically cleared upon completion.
DMA arm channel 2
This bit must be set in order for any DMA transfers to occur on
the channel. For non-repetitive transfer modes, the bit is
automatically cleared upon completion.
DMA arm channel 1
This bit must be set in order for any DMA transfers to occur on
the channel. For non-repetitive transfer modes, the bit is
automatically cleared upon completion.
DMA arm channel 0
This bit must be set in order for any DMA transfers to occur on
the channel. For non-repetitive transfer modes, the bit is
automatically cleared upon completion.
CC2430 Data Sheet (rev. 2.1) SWRS036F
Page 96 of 211