CC2430 Datasheet, PDF (94/212 Pages) Texas Instruments – A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee-TM

CC2430
DMA
Trigger
number
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
DMA Trigger
name
Peripherals : DMA Controller
Table 41: DMA Trigger Sources
Functional unit
Description
NONE
PREV
T1_CH0
T1_CH1
T1_CH2
T2_COMP
T2_OVFL
T3_CH0
T3_CH1
T4_CH0
T4_CH1
ST
IOC_0
IOC_1
URX0
UTX0
URX1
UTX1
FLASH
RADIO
ADC_CHALL
ADC_CH11
ADC_CH21
ADC_CH32
ADC_CH42
ADC_CH53
ADC_CH63
ADC_CH74
ADC_CH84
ENC_DW
ENC_UP
DMA
DMA
Timer 1
Timer 1
Timer 1
Timer 2
Timer 2
Timer 3
Timer 3
Timer 4
Timer 4
Sleep Timer
IO Controller
IO Controller
USART0
USART0
USART1
USART1
Flash
controller
Radio
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
AES
AES
No trigger, setting DMAREQ.DMAREQx bit starts transfer
DMA channel is triggered by completion of previous channel
Timer 1, compare, channel 0
Timer 1, compare, channel 1
Timer 1, compare, channel 2
Timer 2, compare
Timer 2, overflow
Timer 3, compare, channel 0
Timer 3, compare, channel 1
Timer 4, compare, channel 0
Timer 4, compare, channel 1
Sleep Timer compare
Port 0 I/O pin input transition⁹
Port 1 I/O pin input transition⁹
USART0 RX complete
USART0 TX complete
USART1 RX complete
USART1 TX complete
Flash data write complete
RF packet byte received/transmit
ADC end of a conversion in a sequence, sample ready
ADC end of conversion channel 0 in sequence, sample ready
ADC end of conversion channel 1 in sequence, sample ready
ADC end of conversion channel 2 in sequence, sample ready
ADC end of conversion channel 3 in sequence, sample ready
ADC end of conversion channel 4 in sequence, sample ready
ADC end of conversion channel 5 in sequence, sample ready
ADC end of conversion channel 6 in sequence, sample ready
ADC end of conversion channel 7 in sequence, sample ready
AES encryption processor requests download input data
AES encryption processor requests upload output data
9 _{Using this trigger source must be aligned with port interrupt enable bits, PICTL.P0IENL/H and}
P1IEN. Note that all interrupt enabled port pins will generate a trigger and the trigger is generated on
each level change on the enabled input (0-1 gives a trigger as does 1-0).
CC2430 Data Sheet (rev. 2.1) SWRS036F
Page 94 of 211