CC2430 Datasheet, PDF (134/212 Pages) Texas Instruments – A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee-TM

CC2430
Peripherals : Random Number Generator
13.11 Random Number Generator
13.11.1 Introduction
The random number generator has the
following features.
• Generate pseudo-random bytes which can
be read by the CPU or used directly by the
Command Strobe Processor (see section
14.34).
• Calculate CRC16 of bytes that are written
to RNDH.
• Seeded by value written to RNDL.
The random number generator is a 16-bit
Linear Feedback Shift Register (LFSR) with
polynomial X ¹⁶ + X ¹⁵ + X ² + 1 (i.e. CRC16).
It uses different levels of unrolling depending
on the operation it performs. The basic version
(no unrolling) is shown in Figure 27.
The random number generator is turned off
when ADCCON1.RCTRL= 11.
15
+
14 13 12 11 10
9
8
7
6
5
4
3
2
+
1
0
in_bit
+
Figure 27: Basic structure of the Random Number Generator
13.11.2 Random Number Generator Operation
The operation of the random number
generator is controlled by the
ADCCON1.RCTRL bits. The current value of the
13.11.2.1 Semi random sequence generation
The default operation (ADCCON1.RCTRL is
00) is to clock the LFSR once (13x unrolling)
each time the Command Strobe Processor
reads the random value. This leads to the
availability of a fresh pseudo-random byte from
the LSB end of the LFSR.
13.11.2.2 Seeding
The LFSR can be seeded by writing to the
RNDL register twice. Each time the RNDL
register is written, the 8 LSB of the LFSR is
copied to the 8 MSB and the 8 LSBs are
replaced with the new data byte that was
written to RNDL.
When a true random value is required, the
LFSR should be seeded by writing RNDL with
random values from the IF_ADC in the RF
receive path. To use this seeding method, the
radio must first be powered on by enabling the
13.11.2.3 CRC16
The LFSR can also be used to calculate the
CRC value of a sequence of bytes. Writing to
the RNDH register will trigger a CRC
calculation. The new byte is processed from
the MSB end and an 8x unrolling is used, so
that a new byte can be written to RNDH every
clock cycle.
16-bit shift register in the LFSR can be read
from the RNDH and RNDL registers.
Another way to update the LFSR is to set
ADCCON1.RCTRL is 01. This will clock the
LFSR once (no unrolling) and the
ADCCON1.RCTRL bits will automatically be
cleared when the operation has completed.
voltage regulator as described in section 15.1.
The radio should be placed in infinite TX state,
to avoid possible sync detect in RX state. The
random values from the IF_ADC are read from
the RF registers ADCTSTH and ADCTSTL (see
page 196). The values read are used as the
seed values to be written to the RNDL register
as described above. Note that this can not be
done while radio is in use for normal tasks.
Note that the LFSR must be properly seeded
by writing to RNDL, before the CRC
calculations start. Usually the seed value
should be 0x0000 or 0xFFFF.
CC2430 Data Sheet (rev. 2.1) SWRS036F
Page 134 of 211