CC2430 Datasheet, PDF (118/212 Pages) Texas Instruments – A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee-TM

CC2430
Peripherals : 8-bit timers, Timer 3 and Timer 4
13.8.3 Channel Mode Control
The channel modes for each channel; 0 and 1,
are set by the control and status registers
13.8.4 Output Compare Mode
In output compare mode the I/O pin associated
with a channel shall be set to an output. After
the timer has been started, the content of the
counter is compared with the contents of the
channel compare register TxCC0n. If the
compare register equals the counter contents,
the output pin is set, reset or toggled according
to the compare output mode setting of
TxCCTL.CMP1:0. Note that all edges on
output pins are glitch-free when operating in a
given compare output mode.
For simple PWM use, output compare modes
4 and 5 are preferred.
TxCCTLn where n is the channel number, 0 or
1. The settings include output compare modes.
Writing to the compare register TxCC0 does
not take effect on the output compare value
until the counter value is 0x00. Writing to the
compare register TxCC1 takes effect
immediately.
When a compare occurs the interrupt flag
corresponding to the actual channel is set.
This is TIMIF.TxCHnIF. An interrupt request
is generated if the corresponding interrupt
mask bit TxCCTLn.IM is set.
13.8.5 Timer 3 and 4 interrupts
There is one interrupt vector assigned to each
of the timers. These are T3 and T4. An
interrupt request is generated when one of the
following timer events occur:
• Counter reaches terminal count value.
• Output compare event
The SFR register TIMIF contains all interrupt
flags for Timer 3 and Timer 4. The register bits
TIMIF.TxOVFIF and TIMIF.TxCHnIF,
contains the interrupt flags for the two terminal
13.8.6 Timer 3 and Timer 4 DMA triggers
There are two DMA triggers associated with
Timer 3 and two DMA triggers associated with
Timer 4. These are the following:
• T3_CH0 : Timer 3 channel 0 compare
• T3_CH1 : Timer 3 channel 1 compare
13.8.7 Timer 3 and 4 registers
count value events and the four channel
compare events, respectively. An interrupt
request is only generated when the
corresponding interrupt mask bit is set. If there
are other pending interrupts, the
corresponding interrupt flag must be cleared
by the CPU before a new interrupt request can
be generated. Also, enabling an interrupt mask
bit will generate a new interrupt request if the
corresponding interrupt flag is set.
• T4_CH0 : Timer 4 channel 0 compare
• T4_CH0 : Timer 4 channel 1 compare
Refer to section 13.5 on page 88 for a
description on use of DMA channels.
T3CNT (0xCA) – Timer 3 Counter
Bit Name
7:0 _CNT[7:0]
Reset R/W
0x00 R
Description
Timer count byte. Contains the current value of the 8-bit counter.
CC2430 Data Sheet (rev. 2.1) SWRS036F
Page 118 of 211