CC2430 Datasheet, PDF (112/212 Pages) Texas Instruments – A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee-TM

CC2430
Peripherals : MAC Timer (Timer2)
13.7.4.1
General
The Timer can be started and stopped
synchronously with the 32kHz clock rising
edge. Note this event is derived from a 32kHz
clock signal, but is synchronous with the
32MHz system clock and thus has a period
approximately equal the 32kHz clock period.
13.7.4.2
Timer synchronous stop
After the timer has started running, i.e. entered
timer RUN mode it is stopped synchronously
by writing 0 to T2CNF.RUN when T2CNF.SYNC
is 1. After T2CNF.RUN has been set to 0, the
At the time of a synchronous start the timer is
reloaded with new calculated values for the
timer and overflow count such that it appears
that the timer has not been stopped (e.g. im
PM1/2 mode).
timer will continue running until the 32kHz
clock rising edge is sampled as 1. When this
occurs the timer is stopped and the current
Sleep timer value is stored.
13.7.4.3
Timer synchronous start
When the timer is in the IDLE mode it is
started synchronously by writing 1 to
T2CNF.RUN when T2CNF.SYNC is 1. After
T2CNF.RUN has been set to 1, the timer will
remain in the IDLE mode until the 32kHz clock
rising edge is detected. When this occurs the
timer will first calculate new values for the 16-
bit timer value and for the 20-bit timer overflow
count, based on the current and stored Sleep
timer values and the current 16-bit timer
values. The new MAC Timer and overflow
count values are loaded into the timer and the
timer enters the RUN mode. This synchronous
start process takes 75 clock cycles from the
time when the 32kHz clock rising edge is
sampled high. The synchronous start and stop
function requires that the system clock
frequency is selected to be 32MHz. If the
16MHz clock is selected, there will be an offset
added to the new calculated value.
The method for calculating the new MAC
Timer value and overflow count value is given
below. Due to the fact that the MAC Timer
clock and Sleep timer clocks are
asynchronous with a non-integer clock ratio
there will be an error of maximum ±1 in
calculated timer value compared to the ideal
timer value.
Calculation of new timer value and overflow count value:
N_c = CurrentSleepTimerValue
N _s = StoredSleepTimerValue
K_ck = ClockRatio = 976.5625 ¹⁰
stw = SleepTimerWidth = 24
P = Timer2Period
O_c = CurrentOverflowCountValue
T_c = CurrentTimerValue
T_OH = Overhead = 75
N_t = N_c − N_s
N_t ≤ 0 ⇒ N_d = 2^stw + N_t ; N_t > 0 ⇒ N_d = N_t
C = N_d ⋅ K_ck + T_C + T_OH (Rounded to nearest integer value)
T = C mod P
O
=
(C
−
P
T
)
+
O_C
Timer2Value = T
Timer2OverflowCount = O
10 _{Clock ratio of MAC Timer clock frequency (32 MHz - XOSC) and Sleep timer clock frequency}
(32.768 kHz - XOSC)
For a given Timer 2 period value, P, there is a
maximum duration between Timer2
synchronous stop and start for which the timer
value is correctly updated after starting. The
maximum value is given in terms of the
number of Sleep Timer clock periods, i.e.
32kHz clock periods, T_ST(max):
T_{ST (max)}
≤
(2 ²⁰
−1) × P + T_OH
K _ck
The maximum period controlled by T2CAPHPH
and T2CAPHPL is defined when thes registers
are 0x0000. When operation in power modes
PM1 or PM2 this will always result in an
overflow and both overflow and timer counter
will be sett to 0xFFFF. The value 0x0000 in
CC2430 Data Sheet (rev. 2.1) SWRS036F
Page 112 of 211