CC2430 Datasheet, PDF (25/212 Pages) Texas Instruments – A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee-TM

9.1 CPU and Peripherals
The 8051 CPU core is a single-cycle 8051-
compatible core. It has three different memory
access buses (SFR, DATA and
CODE/XDATA), a debug interface and an 18-
input extended interrupt unit. See section 11
for details on the CPU.
The memory crossbar/arbitrator is at the
heart of the system as it connects the CPU
and DMA controller with the physical
memories and all peripherals through the SFR
bus. The memory arbitrator has four memory
access points, access at which can map to
one of three physical memories: an 8 KB
SRAM, flash memory or RF and SFR
registers. The memory arbitrator is responsible
for performing arbitration and sequencing
between simultaneous memory accesses to
the same physical memory.
The SFR bus is drawn conceptually in Figure
5 as a common bus that connects all hardware
peripherals to the memory arbitrator. The SFR
bus in the block diagram also provides access
to the radio registers in the radio register bank
even though these are indeed mapped into
XDATA memory space.
The 8 KB SRAM maps to the DATA memory
space and to parts of the XDATA memory
spaces. 4 KB of the 8 KB SRAM is an ultra-
low-power SRAM that retains its contents even
when the digital part is powered off (power
modes 2 and 3). The rest of the SRAM loses
its contents when the digital part is powered
off.
The 32/64/128 KB flash block provides in-
circuit programmable non-volatile program
memory for the device and maps into the
CODE and XDATA memory spaces. Table 22
shows the available devices in the CC2430
family. The available devices differ only in
flash memory size. Writing to the flash block is
performed through a flash controller that
allows page-wise (2048 byte) erasure and 4
byte-wise programming. See section 13.3 for
details on the flash controller.
A versatile five-channel DMA controller is
available in the system and accesses memory
using the XDATA memory space and thus has
access to all physical memories. Each channel
is configured (trigger, priority, transfer mode,
addressing mode, source and destination
pointers, and transfer count) with DMA
descriptors anywhere in memory. Many of the
hardware peripherals rely on the DMA
controller for efficient operation (AES core,
flash write controller, USARTs, Timers, ADC
interface) by performing data transfers
CC2430
between a single SFR address and
flash/SRAM. See section 13.5 for details.
The interrupt controller services a total of 18
interrupt sources, divided into six interrupt
groups, each of which is associated with one
of four interrupt priorities. An interrupt request
is serviced even if the device is in a sleep
mode (power modes 1-3) by bringing the
CC2430 back to active mode (power mode 0).
The debug interface implements a proprietary
two-wire serial interface that is used for in-
circuit debugging. Through this debug
interface it is possible to perform an erasure of
the entire flash memory, control which
oscillators are enabled, stop and start
execution of the user program, execute
supplied instructions on the 8051 core, set
code breakpoints, and single step through
instructions in the code. Using these
techniques it is possible to elegantly perform
in-circuit debugging and external flash
programming. See section 12 for details.
The I/O-controller is responsible for all
general-purpose I/O pins. The CPU can
configure whether peripheral modules control
certain pins or whether they are under
software control, and if so whether each pin is
configured as an input or output and if a pull-
up or pull-down resistor in the pad is
connected. Each peripheral that connects to
the I/O-pins can choose between two different
I/O pin locations to ensure flexibility in various
applications. See section 13.4 for details.
The sleep timer is an ultra-low power timer
that counts 32.768 kHz crystal oscillator or 32
kHz RC oscillator periods. The sleep timer
runs continuously in all operating modes
except power mode 3. Typical uses for it is as
a real-time counter that runs regardless of
operating mode (except power mode 3) or as a
wakeup timer to get out of power mode 1 or 2.
See section 13.9 for details.
A built-in watchdog timer allows the CC2430
to reset itself in case the firmware hangs.
When enabled by software, the watchdog
timer must be cleared periodically, otherwise it
will reset the device when it times out. See
section 13.13 for details.
Timer 1 is a 16-bit timer with
timer/counter/PWM functionality. It has a
programmable prescaler, a 16-bit period value
and three individually programmable
counter/capture channels each with a 16-bit
compare value. Each of the counter/capture
channels can be used as PWM outputs or to
CC2430 Data Sheet (rev. 2.1) SWRS036F
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