CC2430 Datasheet, PDF(101/212 Page) Texas Instruments – A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee-TM

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CC2430 Datasheet, PDF (101/212 Pages) Texas Instruments – A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee-TM

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Peripherals : 16-bit timer, Timer1

T1CC0

CC2430

0000h

OVFL

Figure 22 : Up/down mode

13.6.6 Channel Mode Control

The channel mode is set with each channelâs

control and status register T1CCTLn. The

13.6.7 Input Capture Mode

When a channel is configured as an input

capture channel, the I/O pin associated with

that channel, is configured as an input. After

the timer has been started, a rising edge,

falling edge or any edge on the input pin will

trigger a capture of the 16-bit counter contents

into the associated capture register. Thus the

timer is able to capture the time when an

external event takes place.

Note: Before an I/O pin can be used by the

timer, the required I/O pin must be configured

as a Timer 1 peripheral pin as described in

section 13.4.5 on page 79 .

settings include input capture and output

compare modes.

The channel input pin is synchronized to the

internal system clock. Thus pulses on the input

pin must have a minimum duration greater

than the system clock period.

The contents of the 16-bit capture register is

read out from registers T1CCnH:T1CCnL.

When the capture takes place the IRCON.T1IF

flag is set together with the interrupt flag for

the channel is set. These bits are

T1CTL.CH0IF for channel 0, T1CTL.CH1IF

for channel 1, and T1CTL.CH2IF for channel

2. An interrupt request is generated if the

corresponding interrupt mask bit on

T1CCTL0.IM, T1CCTL1.IM, or T1CCTL2.IM,

respectively, is set together with IEN1.T1EN.

13.6.8 Output Compare Mode

In output compare mode the I/O pin associated

with a channel is set as an output. After the

timer has been started, the contents of the

counter are compared with the contents of the

channel compare register T1CCnH:T1CCnL. If

the compare register equals the counter

contents, the output pin is set, reset or toggled

according to the compare output mode setting

of T1CCTLn.CMP. Note that all edges on

output pins are glitch-free when operating in a

given output compare mode. Writing to the

compare register T1CCnL is buffered so that a

value written to T1CCnL does not take effect

until the corresponding high order register,

T1CCnH is written. For output compare modes

1-3, a new value written to the compare

registers have been written. For other output

compare modes the new value written to the

compare register takes effect when the timer

reaches 0x0000.

Note that channel 0 has fewer output compare

modes because T1CC0H:T1CC0L has a

special function in modes 6 and 7, meaning

these modes would not be useful for channel

When a compare occurs, the interrupt flag for

the channel is set. These bits are

T1CTL.CH0IF for channel 0, T1CTL.CH1IF

for channel 1, and T1CTL.CH2IF for channel

2, and the common interrupt flag

IRCON.T1IF. An interrupt request is

generated if the corresponding interrupt mask

bit on T1CCTL0.IM, T1CCTL1.IM, or

T1CCTL2.IM, respectively, is set together with

IRCON.T1IF. When operating in up-down

mode, the interrupt flag for channel 0 is set

CC2430 Data Sheet (rev. 2.1) SWRS036F

Page 101 of 211

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