C8051F50X_11 Datasheet, PDF (97/313 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F50x/F51x
12. Memory Organization
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are
two separate memory spaces: program memory and data memory. Program and data memory share the
same address space but are accessed via different instruction types. The memory organization is shown in
Figure 12.1
PROGRAM/DATA MEMORY
(FLASH)
C8051F500/1/2/3/8/9
0xFF
0xFC00
0xFBFF
RESERVED
0x80
0x7F
64 kB FLASH
(In-System
Programmable in 512
Byte Sectors)
0x30
0x2F
0x20
0x1F
0x00
DATA MEMORY (RAM)
INTERNAL DATA ADDRESS SPACE
Upper 128 RAM
(Indirect Addressing
Only)
Special Function
Register's
(Direct Addressing Only)
(Direct and Indirect
Addressing)
Bit Addressable
General Purpose
Registers
Lower 128 RAM
(Direct and Indirect
Addressing)
0x0000
C8051F504/5/6/7-F510/1
0x7FFF
32 kB FLASH
(In-System
Programmable in 512
Byte Sectors)
0x0000
EXTERNAL DATA ADDRESS SPACE
0xFFFF
Same 4096 bytes as
from 0x0000 to 0x0FFF,
wrapped on 4096-byte
boundaries
0x1000
0x0FFF
0x0000
XRAM
4K Bytes
(accessable using
MOVX instruction)
Figure 12.1. C8051F50x/F51x Memory Map
Rev. 1.2
97