C8051F50X_11 Datasheet, PDF (188/313 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F50x/F51x
SFR Definition 20.6. P1MASK: Port 1 Mask Register
Bit
7
6
5
4
3
2
1
0
Name
P1MASK[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xF4; SFR Page = 0x00
Bit
Name
Function
7:0 P1MASK[7:0] Port 1 Mask Value.
Selects P1 pins to be compared to the corresponding bits in P1MAT.
0: P1.n pin logic value is ignored and cannot cause a Port Mismatch event.
1: P1.n pin logic value is compared to P1MAT.n.
SFR Definition 20.7. P1MAT: Port 1 Match Register
Bit
7
6
5
4
3
2
1
0
Name
P1MAT[7:0]
Type
R/W
Reset
1
1
1
1
1
1
1
1
SFR Address = 0xF3; SFR Page = 0x00
Bit
Name
Function
7:0 P1MAT[7:0] Port 1 Match Value.
Match comparison value used on Port 1 for bits in P1MAT which are set to 1.
0: P1.n pin logic value is compared with logic LOW.
1: P1.n pin logic value is compared with logic HIGH.
188
Rev. 1.2