C8051F50X_11 Datasheet, PDF (62/313 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F50x/F51x
Gain Register Definition 6.3. ADC0GNA: ADC0 Additional Selectable Gain
Bit
Name
Type
Reset
7
Reserved
W
0
6
Reserved
W
0
5
Reserved
W
0
4
Reserved
W
0
3
Reserved
W
0
2
Reserved
W
0
1
Reserved
W
0
0
GAINADD
W
1
Indirect Address = 0x08;
Bit Name
7:1 Reserved Must Write 0000000b.
Function
0 GAINADD ADC0 Additional Gain Bit.
Setting this bit add 1/64 (0.016) gain to the gain value in the ADC0GNH and
ADC0GNL registers.
Note: This register is accessed indirectly; See Section 6.3.2 for details for writing this register.
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Rev. 1.2