C8051F50X_11 Datasheet, PDF (230/313 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F50x/F51x
Table 23.1. SMBus Clock Source Selection
SMBCS1
0
0
1
1
SMBCS0
0
1
0
1
SMBus Clock Source
Timer 0 Overflow
Timer 1 Overflow
Timer 2 High Byte Overflow
Timer 2 Low Byte Overflow
The SMBCS1–0 bits select the SMBus clock source, which is used only when operating as a master or
when the Free Timeout detection is enabled. When operating as a master, overflows from the selected
source determine the absolute minimum SCL low and high times as defined in Equation 23.1. Note that the
selected clock source may be shared by other peripherals so long as the timer is left running at all times.
For example, Timer 1 overflows may generate the SMBus and UART baud rates simultaneously. Timer
configuration is covered in Section “26. Timers” on page 265.
T_HighMin
=
T_LowMin
=
------------------------¹-------------------------
f_{ClockSourceOverflow}
Equation 23.1. Minimum SCL High and Low Times
The selected clock source should be configured to establish the minimum SCL High and Low times as per
Equation 23.1. When the interface is operating as a master (and SCL is not driven or extended by any
other devices on the bus), the typical SMBus bit rate is approximated by Equation 23.2.
BitRate
=
f_{--C----l-o---c--k---S---o---u---r--c--e---O----v--e---r--f-l-o---w--}
3
Equation 23.2. Typical SMBus Bit Rate
Figure 23.4 shows the typical SCL generation described by Equation 23.2. Notice that T_HIGH is typically
twice as large as T_LOW. The actual SCL output may vary due to other devices on the bus (SCL may be
extended low by slower slave devices, or driven low by contending master devices). The bit rate when
operating as a master will never exceed the limits defined by equation Equation 23.1.
Timer Source
Overflows
SCL
T_Low
T_High
SCL High Timeout
Figure 23.4. Typical SMBus SCL Generation
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Rev. 1.2