C8051F50X_11 Datasheet, PDF (91/313 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F50x/F51x
Table 11.1. CIP-51 Instruction Set Summary (Prefetch-Enabled)(Continued)
Mnemonic
Description
Bytes
Clock
Cycles
SETB C
SETB bit
CPL C
CPL bit
ANL C, bit
ANL C, /bit
ORL C, bit
ORL C, /bit
MOV C, bit
MOV bit, C
JC rel
JNC rel
JB bit, rel
JNB bit, rel
JBC bit, rel
Set Carry
Set direct bit
Complement Carry
Complement direct bit
AND direct bit to Carry
AND complement of direct bit to Carry
OR direct bit to carry
OR complement of direct bit to Carry
Move direct bit to Carry
Move Carry to direct bit
Jump if Carry is set
Jump if Carry is not set
Jump if direct bit is set
Jump if direct bit is not set
Jump if direct bit is set and clear bit
1
1
2
2
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2/(4-6)^*
2
2/(4-6)*
3
3/(5-7)*
3
3/(5-7)*
3
3/(5-7)*
Program Branching
ACALL addr11
LCALL addr16
RET
RETI
AJMP addr11
LJMP addr16
SJMP rel
JMP @A+DPTR
JZ rel
JNZ rel
CJNE A, direct, rel
CJNE A, #data, rel
CJNE Rn, #data, rel
CJNE @Ri, #data, rel
DJNZ Rn, rel
DJNZ direct, rel
NOP
Absolute subroutine call
2
Long subroutine call
3
Return from subroutine
1
Return from interrupt
1
Absolute jump
2
Long jump
3
Short jump (relative address)
2
Jump indirect relative to DPTR
1
Jump if A equals zero
2
Jump if A does not equal zero
2
Compare direct byte to A and jump if not equal
3
Compare immediate to A and jump if not equal
3
Compare immediate to Register and jump if not 3
equal
Compare immediate to indirect and jump if not
3
equal
Decrement Register and jump if not zero
2
Decrement direct byte and jump if not zero
3
No operation
1
4-6*
5-7*
6-8*
6-8*
4-6*
5-7*
4-6*
3-5*
2/(4-6)*
2/(4-6)*
4/(6-8)*
3/(6-8)*
3/(5-7)*
4/(6-8)*
2/(4-6)*
3/(5-7)*
1
Note: Certain instructions take a variable number of clock cycles to execute depending on instruction alignment and
the FLRT setting (SFR Definition 15.3).
Rev. 1.2
91