C8051F50X_11 Datasheet, PDF (299/313 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F50x/F51x
Table 27.3. Watchdog Timer Timeout Intervals¹
System Clock (Hz)
PCA0CPL5 Timeout Interval (ms)
24,000,000
255
32.8
24,000,000
128
16.5
24,000,000
32
4.2
3,000,000
255
3,000,000
128
262.1
132.1
3,000,000
32
187,500²
255
187,500²
128
187,500²
32
33.8
4194
2114
541
Notes:
1. Assumes SYSCLK/12 as the PCA clock source, and a PCA0L value
of 0x00 at the update time.
2. Internal SYSCLK reset frequency = Internal Oscillator divided by
128.
Rev. 1.2
299