C8051F50X_11 Datasheet, PDF (114/313 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F50x/F51x
Table 13.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
Address
Description
IT01CF
0xE4
INT0/INT1 Configuration
LIN0ADR
0xD3
LIN0 Address
LIN0CF
0xC9
LIN0 Configuration
LIN0DAT
0xD2
LIN0 Data
OSCICN
0xA1
Internal Oscillator Control
OSCICRS
OSCIFIN
OSCXCN
0xA2
0x9E
0x9F
Internal Oscillator Coarse Control
Internal Oscillator Fine Calibration
External Oscillator Control
P0
0x80
Port 0 Latch
P0MASK
0xF2
Port 0 Mask Configuration
P0MAT
0xF1
Port 0 Match Configuration
P0MDIN
0xF1
Port 0 Input Mode Configuration
P0MDOUT
0xA4
Port 0 Output Mode Configuration
P0SKIP
0xD4
Port 0 Skip
P1
0x90
Port 1 Latch
P1MASK
0xF4
Port 1 Mask Configuration
P1MAT
0xF3
Port 1 Match Configuration
P1MDIN
0xF2
Port 1 Input Mode Configuration
P1MDOUT
0xA5
Port 1 Output Mode Configuration
P1SKIP
0xD5
Port 1 Skip
P2
0xA0
Port 2 Latch
P2MASK
P2MAT
0xB2
0xB1
Port 2 Mask Configuration
Port 2 Match Configuration
P2MDIN
0xF3
Port 2 Input Mode Configuration
P2MDOUT
0xA6
Port 2 Output Mode Configuration
P2SKIP
0xD6
Port 2 Skip
P3
0xB0
Port 3 Latch
P3MASK
0xAF
Port 3 Mask Configuration
P3MAT
P3MDIN
P3MDOUT
0xAE
0xF4
0xAE
Port 3 Match Configuration
Port 3 Input Mode Configuration
Port 3 Output Mode Configuration
P3SKIP
0xD7
Port 3 Skip
P4
0xB5
Port 4 Latch
P4MDOUT
0xAF
Port 4 Output Mode Configuration
PCA0CN
0xD8
PCA Control
PCA0CPH0
0xFC
PCA Capture 0 High
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