C8051F50X_11 Datasheet, PDF (116/313 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F50x/F51x
Table 13.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
Address
Description
SMB0CF
0xC1
SMBus0 Configuration
SMB0CN
0xC0
SMBus0 Control
SMB0DAT
SMOD0
SN0 - SN3
SP
SPI0CFG
SPI0CKR
SPI0CN
SPI0DAT
TCON
0xC2
0xA9
0xF9 - 0xFC
0x81
0xA1
0xA2
0xF8
0xA3
0x88
SMBus0 Data
UART0 Mode
Serial Number Registers
Stack Pointer
SPI0 Configuration
SPI0 Clock Rate Control
SPI0 Control
SPI0 Data
Timer/Counter Control
TH0
TH1
TL0
TL1
TMOD
TMR2CN
TMR2H
TMR2L
TMR2RLH
0x8C
0x8D
0x8A
0x8B
0x89
0xC8
0xCD
0xCC
0xCB
Timer/Counter 0 High
Timer/Counter 1 High
Timer/Counter 0 Low
Timer/Counter 1 Low
Timer/Counter Mode
Timer/Counter 2 Control
Timer/Counter 2 High
Timer/Counter 2 Low
Timer/Counter 2 Reload High
TMR2RLL
0xCA
Timer/Counter 2 Reload Low
TMR3CN
TMR3H
TMR3L
TMR3RLH
TMR3RLL
VDM0CN
XBR0
XBR1
XBR2
0x91
0x95
0x94
0x93
0x92
0xFF
0xE1
0xE2
0xC7
Timer/Counter 3 Control
Timer/Counter 3 High
Timer/Counter 3 Low
Timer/Counter 3 Reload High
Timer/Counter 3 Reload Low
V_DD Monitor Control
Port I/O Crossbar Control 0
Port I/O Crossbar Control 1
Port I/O Crossbar Control 2
Page
232
234
236
249
96
94
259
261
260
261
271
274
274
273
273
272
278
280
280
279
279
284
286
286
285
285
144
184
185
186
Note: The CAN registers are not explicitly defined in this datasheet. See Table 22.2 on page 223 for the list of all
available CAN registers.
116
Rev. 1.2