C8051F50X_11 Datasheet, PDF (32/313 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F50x/F51x
4.2. QFN-48 Package Specifications
Figure 4.3. QFN-48 Package Drawing
Table 4.3. QFN-48 Package Dimensions
Dimension Min
Typ
Max
Dimension Min
Typ
Max
A
0.80
0.90
1.00
A1
0.00
-
0.05
b
0.18
0.23
0.30
D
7.00 BSC
D2
3.90
4.00
4.10
e
0.50 BSC
E
7.00 BSC
E2
3.90
4.00
4.10
L
0.30
0.40
0.50
L1
0.00
-
0.08
aaa
-
-
0.10
bbb
-
-
0.10
ddd
-
-
0.05
eee
-
-
0.08
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-220, variation VKKD-4 except for features D2 and L
which are toleranced per supplier designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
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Rev. 1.2