C8051F50X_11 Datasheet, PDF (311/313 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F50x/F51x
Revision 1.1 to Revision 1.2
 Updated “1. System Overview” with a voltage range specification for the internal oscillator.
 Updated Table 5.6 on page 47 with new conditions for the internal oscillator accuracy. The internal
oscillator accuracy is dependent on the operating voltage range.
 Updated “5. Electrical Characteristics” to remove the internal oscillator curve across temperature
diagram.
 Updated SFR Definition 10.1 (REG0CN) with a new definition for Bit 6. The bit 6 reset value is 1b and
must be written to 1b.
 Updated “21. Local Interconnect Network (LIN)” with a voltage range specification for the internal
oscillator.
 Updated “22. Controller Area Network (CAN0)” with a voltage range specification for the internal
oscillator.
 Updated SFR Definition 8.1 (REF0CN) with oscillator suspend requirement for ZTCEN.
 Updated "16.3 Suspend Mode" with note regarding ZTCEN.
 Updated Figure 6.4 with new timing diagram when using CNVSTR pin.
 Added Port 2 Event and Port 3 Events to wake-up sources in Section 19.2.1.
 Updated LIN Register Definitions 21.9 and 21.10 with correct reset values.
 Updated C2 Register Definitions 28.2 and 28.3 with correct C2 and SFR addresses.
Rev. 1.2
311