C8051F50X_11 Datasheet, PDF (198/313 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F50x/F51x
SFR Definition 20.25. P3MDIN: Port 3 Input Mode
Bit
7
6
5
4
3
2
1
0
Name
P3MDIN[7:0]
Type
R/W
Reset
1
1
1
1
1
1
1
1
SFR Address = 0xF4; SFR Page = 0x0F
Bit
Name
Function
7:0 P3MDIN[7:0] Analog Configuration Bits for P3.7–P3.0 (respectively).
Port pins configured for analog mode have their weak pull-up and digital receiver
disabled. For analog mode, the pin also needs to be configured for open-drain
mode in the P3MDOUT register.
0: Corresponding P3.n pin is configured for analog mode.
1: Corresponding P3.n pin is not configured for analog mode.
Note: Port P3.1–P3.7 are only available on the 48-pin and 40-pin packages.
SFR Definition 20.26. P3MDOUT: Port 3 Output Mode
Bit
7
6
5
4
3
2
1
0
Name
P3MDOUT[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xAE; SFR Page = 0x0F
Bit
Name
Function
7:0 P3MDOUT[7:0] Output Configuration Bits for P3.7–P3.0 (respectively).
These bits are ignored if the corresponding bit in register P3MDIN is logic 0.
0: Corresponding P3.n Output is open-drain.
1: Corresponding P3.n Output is push-pull.
Note: Port P3.1–P3.7 are only available on the and 40-pin 48-pin packages.
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Rev. 1.2