C8051F50X_11 Datasheet, PDF (264/313 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F50x/F51x
Table 25.1. SPI Slave Timing Parameters
Parameter Description
Min
Max
Units
Master Mode Timing^* (See Figure 25.8 and Figure 25.9)
T_MCKH
T_MCKL
T_MIS
SCK High Time
SCK Low Time
MISO Valid to SCK Shift Edge
1 x T_SYSCLK
—
ns
1 x T_SYSCLK
—
ns
1 x T_SYSCLK + 20
—
ns
T_MIH
SCK Shift Edge to MISO Change
0
—
ns
Slave Mode Timing^* (See Figure 25.10 and Figure 25.11)
T_SE
NSS Falling to First SCK Edge
2 x T_SYSCLK
—
ns
T_SD
Last SCK Edge to NSS Rising
2 x T_SYSCLK
—
ns
T_SEZ
T_SDZ
NSS Falling to MISO Valid
NSS Rising to MISO High-Z
—
4 x T_SYSCLK ns
—
4 x T_SYSCLK ns
T_CKH
T_CKL
T_SIS
SCK High Time
SCK Low Time
MOSI Valid to SCK Sample Edge
5 x T_SYSCLK
5 x T_SYSCLK
2 x T_SYSCLK
—
ns
—
ns
—
ns
T_SIH
T_SOH
T_SLH
SCK Sample Edge to MOSI Change
SCK Shift Edge to MISO Change
Last SCK Edge to MISO Change 
(CKPHA = 1 ONLY)
2 x T_SYSCLK
—
6 x T_SYSCLK
—
ns
4 x T_SYSCLK ns
8 x T_SYSCLK ns
*Note: T_SYSCLK is equal to one period of the device system clock (SYSCLK).
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Rev. 1.2