C8051F50X_11 Datasheet, PDF (23/313 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F50x/F51x
Table 3.1. Pin Definitions for the C8051F50x/F51x(Continued)
Name
Pin
‘F500/1/4/5
(48-pin)
Pin
F508/9-
F510/1
(40-pin)
Pin
‘F502/3/6/7
(32-pin)
Type
Description
P0.6
44
36
28 D I/O or A In Port 0.6
P0.7
43
35
27 D I/O or A In Port 0.7
P1.0
42
34
26 D I/O or A In Port 1.0. See SFR Definition 20.16 for a
description.
P1.1
41
33
25 D I/O or A In Port 1.1.
P1.2
40
32
24 D I/O or A In Port 1.2.
P1.3
39
31
23 D I/O or A In Port 1.3.
P1.4
38
30
22 D I/O or A In Port 1.4.
P1.5
37
29
21 D I/O or A In Port 1.5.
P1.6
36
28
20 D I/O or A In Port 1.6.
P1.7
35
27
19 D I/O or A In Port 1.7.
P2.0
34
26
18 D I/O or A In Port 2.0. See SFR Definition 20.20 for a
description.
P2.1
33
25
17 D I/O or A In Port 2.1.
P2.2
32
24
16 D I/O or A In Port 2.2.
P2.3
31
23
15 D I/O or A In Port 2.3.
P2.4
30
22
14 D I/O or A In Port 2.4.
P2.5
29
21
13 D I/O or A In Port 2.5.
P2.6
28
20
12 D I/O or A In Port 2.6.
P2.7
27
19
11 D I/O or A In Port 2.7.
P3.0
26
18
— D I/O or A In Port 3.0. See SFR Definition 20.24 for a
description.
P3.1
25
17
— D I/O or A In Port 3.1.
P3.2
24
16
— D I/O or A In Port 3.2.
P3.3
23
15
— D I/O or A In Port 3.3.
P3.4
22
14
— D I/O or A In Port 3.4.
P3.5
21
13
— D I/O or A In Port 3.5.
P3.6
20
12
— D I/O or A In Port 3.6.
Rev. 1.2
23