C8051F50X_11 Datasheet, PDF (197/313 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F50x/F51x
SFR Definition 20.23. P2SKIP: Port 2 Skip
Bit
7
6
5
4
3
2
1
0
Name
P2SKIP[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xD6; SFR Page = 0x0F
Bit
Name
Function
7:0 P2SKIP[7:0] Port 2 Crossbar Skip Enable Bits.
These bits select Port 2 pins to be skipped by the Crossbar Decoder. Port pins
used for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P2.n pin is not skipped by the Crossbar.
1: Corresponding P2.n pin is skipped by the Crossbar.
SFR Definition 20.24. P3: Port 3
Bit
7
6
5
4
3
2
1
0
Name
P3[7:0]
Type
R/W
Reset
1
1
1
1
1
1
1
1
SFR Address = 0xB0; SFR Page = All Pages; Bit-Addressable
Bit Name
Description
Write
7:0 P3[7:0] Port 3 Data.
0: Set output latch to logic
Sets the Port latch logic
LOW.
value or reads the Port pin ^{1: Set output latch to logic}
logic state in Port cells con- ^HIGH.
figured for digital I/O.
Read
0: P3.n Port pin is logic
LOW.
1: P3.n Port pin is logic
HIGH.
Note: Port P3.1–P3.7 are only available on the 48-pin and 40-pin packages.
Rev. 1.2
197