C8051F50X_11 Datasheet, PDF (182/313 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F50x/F51x
P o rt
P0
P1
P2
P3
P4
S pe cia l
F u n c ti o n
S igna ls
P 3.1-P 3.7, P 4.0 only
available on the 48-pin
and 40-pin pac k ages
P 4.1-P 4.7 only
available on the 48-
pin packages
PIN I/O
0123456701234567012345670123456701234567
UART_TX
UART_RX
CAN_TX
CAN_RX
SCK
M IS O
MOSI
NSS
*NS S Is only pinned out in 4-wire S P I M ode
SDA
SCL
CP0
CP 0A
CP1
CP 1A
S YS CL K
CEX 0
CEX 1
CEX 2
CEX 3
CEX 4
CEX 5
ECI
T0
T1
LIN_TX
LIN_RX
01100100000000000000000000000000
P 0S KIP [0:7]
P 1S KIP [0:7]
P 2S KIP [0:7]
P 3S KIP [0:7]
Figure 20.4. Crossbar Priority Decoder in Example Configuration
20.4. Port I/O Initialization
Port I/O initialization consists of the following steps:
1. Select the input mode (analog or digital) for all Port pins, using the Port Input Mode register (PnMDIN).
2. Select the output mode (open-drain or push-pull) for all Port pins, using the Port Output Mode register
(PnMDOUT).
3. Select any pins to be skipped by the I/O Crossbar using the Port Skip registers (PnSKIP).
4. Assign Port pins to desired peripherals.
5. Enable the Crossbar (XBARE = 1).
All Port pins must be configured as either analog or digital inputs. Port 4 on the C8051F500/1/4/5 and
C8051F508/9-F510/1 is a digital-only Port. Any pins to be used as Comparator or ADC inputs should be
configured as an analog inputs. When a pin is configured as an analog input, its weak pullup, digital driver,
and digital receiver are disabled. This process saves power and reduces noise on the analog input. Pins
configured as digital inputs may still be used by analog peripherals; however this practice is not recom-
mended.
Additionally, all analog input pins should be configured to be skipped by the Crossbar (accomplished by
setting the associated bits in PnSKIP). Port input mode is set in the PnMDIN register, where a 1 indicates a
182
Rev. 1.2