C8051F50X_11 Datasheet, PDF (263/313 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F50x/F51x
NSS
T
SE
SCK*
T
CKH
T
CKL
T
SIS
T
SIH
MOSI
MISO
T
SEZ
T
SOH
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
Figure 25.10. SPI Slave Timing (CKPHA = 0)
T
SD
T
SDZ
NSS
T
T
T
SE
CKL
SD
SCK*
T
CKH
T
SIS
T
SIH
MOSI
T
SEZ
MISO
T
SOH
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
T
SLH
T
SDZ
Figure 25.11. SPI Slave Timing (CKPHA = 1)
Rev. 1.2
263