C8051F50X_11 Datasheet, PDF (220/313 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F50x/F51x
The CAN controller clock must be less than or equal to 25 MHz. If the CIP-51 system clock is above
25 MHz, the divider in the CAN0CFG register must be set to divide the CAN controller clock down to an
appropriate speed.
22.1.2. CAN Register Access
The CAN controller clock divider selected in the CAN0CFG SFR affects how the CAN registers can be
accessed. If the divider is set to 1, then a CAN SFR can immediately be read after it is written. If the divider
is set to a value other than 1, then a read of a CAN SFR that has just been written must be delayed by a
certain number of cycles. This delay can be performed using a NOP or some other instruction that does
not attempt to read the register. This access limitation applies to read and read-modify-write instructions
that occur immediately after a write. The full list of affected instructions is ANL, ORL, MOV, XCH, and XRL.
For example, with the CAN0CFG divider set to 1, the CAN0CN SFR can be accessed as follows:
MOV CAN0CN, #041
MOV R7, CAN0CN
; Enable access to Bit Timing Register
; Copy CAN0CN to R7
With the CAN0CFG divider set to /2, the same example code requires an additional NOP:
MOV CAN0CN, #041
; Enable access to Bit Timing Register
NOP
; Wait for write to complete
MOV R7, CAN0CN
; Copy CAN0CN to R7
The number of delay cycles required is dependent on the divider setting. With a divider of 2, the read must
wait for 1 system clock cycle. With a divider of 4, the read must wait 3 system clock cycles, and with the
divider set to 8, the read must wait 7 system clock cycles. The delay only needs to be applied when read-
ing the same register that was written. The application can write and read other CAN SFRs without any
delay.
22.1.3. Example Timing Calculation for 1 Mbit/Sec Communication
This example shows how to configure the CAN controller timing parameters for a 1 Mbit/Sec bit rate. Table
18.1 shows timing-related system parameters needed for the calculation.
Table 22.1. Background System Information
Parameter
Value
Description
CIP-51 system clock (SYSCLK)
CAN controller clock (fsys)
CAN clock period (tsys)
CAN time quantum (tq)
CAN bus length
Propogation delay time³
24 MHz
24 MHz
41.667 ns
41.667 ns
10 m
400 ns
Internal Oscillator Max
CAN0CFG divider set to 1
Derived from 1/fsys
Derived from tsys x BRP^1,2
5 ns/m signal delay between CAN nodes
2 x (transceiver loop delay + bus line delay)
Notes:
1. The CAN time quantum is the smallest unit of time recognized by the CAN controller. Bit timing parameters
are specified in integer multiples of the time quantum.
2. The Baud Rate Prescaler (BRP) is defined as the value of the BRP Extension Register plus 1. The BRP
extension register has a reset value of 0x0000. The BRP has a reset value of 1.
3. Based on an ISO-11898 compliant transceiver. CAN does not specify a physical layer.
Each bit transmitted on a CAN network has 4 segments (Sync_Seg, Prop_Seg, Phase_Seg1, and
Phase_Seg2), as shown in Figure 18.3. The sum of these segments determines the CAN bit time (1/bit
rate). In this example, the desired bit rate is 1 Mbit/sec; therefore, the desired bit time is 1000 ns.
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