C8051F50X_11 Datasheet, PDF (270/313 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F50x/F51x
Pre-scaled Clock
SYSCLK
CKCON
TTTTTTSS
3 3 2 2 1 0CC
MMMMMMA A
HLHL
10
TMOD
GC T TGCT T
A / 11A / 00
T T MM T T MM
E1 1 0E0 1 0
1
0
0
TR1
1
0
1
T0
Crossbar
GATE0
TR0
TH0
(8 bits)
TL0
(8 bits)
/INT0
IN0PL _XOR
Figure 26.3. T0 Mode 3 Block Diagram
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Interrupt
Interrupt
270
Rev. 1.2