C8051F50X_11 Datasheet, PDF (20/313 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F50x/F51x
2. Ordering Information
The following features are common to all devices in this family:
 50 MHz system clock and 50 MIPS throughput (peak)
 4352 bytes of RAM (256 internal bytes and 4096 XRAM bytes)
 SMBus/I²C, Enhanced SPI, Enhanced UART
 Four Timers
 Six Programmable Counter Array channels
 Internal 24 MHz oscillator
 Internal Voltage Regulator
 12-bit, 200 ksps ADC
 Internal Voltage Reference and Temperature Sensor
 Two Analog Comparators
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Table 2.1 shows the feature that differentiate the devices in this family.
20
Rev. 1.2