C8051F50X_11 Datasheet, PDF (136/313 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F50x/F51x
SFR Definition 15.3. FLSCL: Flash Scale
Bit
7
6
5
4
3
2
1
0
Name Reserved Reserved Reserved FLRT Reserved Reserved FLEWT Reserved
Type R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xB6; SFR Page = All Pages
Bit Name
7:5 Reserved Must Write 000b.
Function
4
FLRT Flash Read Time Control.
This bit should be programmed to the smallest allowed value, according to the system
clock speed.
0: SYSCLK < 25 MHz (Flash read strobe is one system clock).
1: SYSCLK > 25 MHz (Flash read strobe is two system clocks).
3:2 Reserved Must Write 00b.
1 FLEWT Flash Erase Write Time Control.
This bit should be set to 1b before Writing or Erasing Flash.
0: Short Flash Erase / Write Timing.
1: Extended Flash Erase / Write Timing.
0 Reserved Must Write 0b.
136
Rev. 1.2