C8051F50X_11 Datasheet, PDF (17/313 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F50x/F51x
C2CK/RST
C2D
VREGIN
VDD
GND
VDDA
GNDA
Power On
Reset
Reset
Debug /
Programming
Hardware
CIP-51 8051
Controller Core
up to 64kB Byte Flash
Program Memory
256 Byte RAM
4 kB XRAM
Voltage Regulator
(LDO)
System Clock Setup
XTAL1 XTAL2
Internal Oscillator External Oscillator
Clock Multiplier
SFR
Bus
Port I/O Configuration
Digital Peripherals
UART0
Timers 0,
1, 2, 3
PCA
WDT
LIN 2.1
Priority
Crossbar
Decoder
CAN 2.0B
SPI
I2C
Crossbar Control
External Memory Interface
*On F500/4 Devices
Analog Peripherals
Voltage
Reference _VREF
VDD
VREF
12-bit
200ksps
A
M
U
ADC
X
VDD
VREF
P0 – P3
Temp
Sensor
GND
CP0, CP0A ₊
Comparator 0 ^-
CP1, CP1A ₊
-
Comparator 1
Figure 1.1. C8051F500/1/4/5 Block Diagram
Port 0
Drivers
Port 1
Drivers
Port 2
Drivers
Port 3
Drivers
Port 4
Drivers
VIO
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
Rev. 1.2
17