C8051F300_08 Datasheet, PDF (93/179 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F300/1/2/3/4/5
SFR Definition 10.2. FLKEY: Flash Lock and Key
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0xB7
Bits7–0:
FLKEY: Flash Lock and Key Register
Write:
This register must be written to before Flash writes or erases can be performed. Flash
remains locked until this register is written to with the following key codes: 0xA5, 0xF1. The
timing of the writes does not matter, as long as the codes are written in order. The key codes
must be written for each Flash write or erase operation. Flash will be locked until the next
system reset if the wrong codes are written or if a Flash operation is attempted before the
codes have been written correctly.
Read:
When read, bits 1–0 indicate the current Flash lock state.
00: Flash is write/erase locked.
01: The first key code has been written (0xA5).
10: Flash is unlocked (writes/erases allowed).
11: Flash writes/erases disabled until the next reset.
SFR Definition 10.3. FLSCL: Flash Scale
R/W
FOSE
Bit7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
Reserved Reserved Reserved Reserved Reserved Reserved Reserved 10000000
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0xB6
Bits7:
Bits6–0:
FOSE: Flash One-shot Enable
This bit enables the 50 ns Flash read one-shot. When the Flash one-shot disabled, the
Flash sense amps are enabled for a full clock cycle during Flash reads.
0: Flash one-shot disabled.
1: Flash one-shot enabled.
RESERVED. Read = 0. Must Write 0.
Rev. 2.9
93