C8051F300_08 Datasheet, PDF (149/179 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F300/1/2/3/4/5
SFR Definition 15.3. CKCON: Clock Control
R/W
R/W
R/W
R/W
R/W
—
T2MH T2ML
T1M
T0M
Bit7
Bit6
Bit5
Bit4
Bit3
R/W
R/W
R/W
Reset Value
—
SCA1 SCA0 00000000
Bit2
Bit1
Bit0 SFR Address:
0x8E
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bits1–0:
UNUSED. Read = 0b, Write = don’t care.
T2MH: Timer 2 High Byte Clock Select
This bit selects the clock supplied to the Timer 2 high byte if Timer 2 is configured in split 8-
bit timer mode. T2MH is ignored if Timer 2 is in any other mode.
0: Timer 2 high byte uses the clock defined by the T2XCLK bit in TMR2CN.
1: Timer 2 high byte uses the system clock.
T2ML: Timer 2 Low Byte Clock Select
This bit selects the clock supplied to Timer 2. If Timer 2 is configured in split 8-bit timer
mode, this bit selects the clock supplied to the lower 8-bit timer.
0: Timer 2 low byte uses the clock defined by the T2XCLK bit in TMR2CN.
1: Timer 2 low byte uses the system clock.
T1M: Timer 1 Clock Select.
This select the clock source supplied to Timer 1. T1M is ignored when C/T1 is set to logic 1.
0: Timer 1 uses the clock defined by the prescale bits, SCA1–SCA0.
1: Timer 1 uses the system clock.
T0M: Timer 0 Clock Select.
This bit selects the clock source supplied to Timer 0. T0M is ignored when C/T0 is set to
logic 1.
0: Counter/Timer 0 uses the clock defined by the prescale bits, SCA1–SCA0.
1: Counter/Timer 0 uses the system clock.
UNUSED. Read = 0b, Write = don’t care.
SCA1–SCA0: Timer 0/1 Prescale Bits
These bits control the division of the clock supplied to Timer 0 and/or Timer 1 if configured
to use prescaled clock inputs.
SCA1 SCA0
Prescaled Clock
0
0 System clock divided by 12
0
1 System clock divided by 4
1
0 System clock divided by 48
1
1 External clock divided by 8
Note: External clock divided by 8 is synchronized with the
system clock, and the external clock must be less
than or equal to the system clock to operate in this
mode.
Rev. 2.9
149