C8051F300_08 Datasheet, PDF (27/179 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F300/1/2/3/4/5
4. Pinout and Package Definitions
Table 4.1. Pin Definitions for the C8051F300/1/2/3/4/5
Name
VREF /
Pin
Pin
F300/1/2/3/4/5 F300/1/2/3/4/5
GM
GP
1
5
Type
A In
Description
External Voltage Reference Input.
P0.0
P0.1
2
V_DD
3
XTAL1 /
4
P0.2
XTAL2 /
5
D I/O or Port 0.0. See Section 12 for complete description.
A In
6
D I/O or Port 0.1. See Section 12 for complete description.
A In
7
Power Supply Voltage.
8
A In Crystal Input. This pin is the external oscillator cir-
cuit return for a crystal or ceramic resonator. See
Section 11.2.
D I/O or
A In Port 0.2. See Section 12 for complete description.
10
A Out Crystal Input/Output. For an external crystal or res-
onator, this pin is the excitation driver. This pin is
the external clock input for CMOS, capacitor, or RC
network configurations. See Section 11.2.
P0.3
P0.4
6
P0.5
7
C2CK /
8
D I/O Port 0.3. See Section 12 for complete description.
12
D I/O or Port 0.4. See Section 12 for complete description.
A In
13
D I/O or Port 0.5. See Section 12 for complete description.
A In
14
D I/O Clock signal for the C2 Development Interface.
RST
P0.6 /
9
D I/O
Device Reset. Open-drain output of internal POR or
V_DD monitor. An external source can initiate a sys-
tem reset by driving this pin low for at least 10 µs.
1
D I/O or Port 0.6. See Section 12 for complete description.
A In
CNVSTR
C2D /
10
D I/O ADC External Convert Start Input Strobe.
2
D I/O Data signal for the C2 Development Interface.
P0.7
GND
11
3
N.C. pins for F30x GP packages: 4, 9, 11
D I/O or Port 0.7. See Section 12 for complete description.
A In
Ground.
Rev. 2.9
27