C8051F300_08 Datasheet, PDF (107/179 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F300/1/2/3/4/5
SFR Definition 12.1. XBR0: Port I/O Crossbar Register 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
—
XSKP6 XSKP5 XSKP4 XSKP3 XSKP2 XSKP1 XSKP0 00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0xE1
Bit7:
Bits6–0:
UNUSED. Read = 0b; Write = don’t care.
XSKP[6:0]: Crossbar Skip Enable Bits
These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as ana-
log inputs (for ADC or Comparator) or used as special functions (VREF input, external oscil-
lator circuit, CNVSTR input) should be skipped by the Crossbar.
0: Corresponding P0.n pin is not skipped by the Crossbar.
1: Corresponding P0.n pin is skipped by the Crossbar.
SFR Definition 12.2. XBR1: Port I/O Crossbar Register 1
R/W
R/W
PCA0ME
Bit7
Bit6
R/W
R/W
CP0AOEN CP0OEN
Bit5
Bit4
R/W
R/W
R/W
SYSCKE SMB0OEN URX0EN
Bit3
Bit2
Bit1
R/W
Reset Value
UTX0EN 00000000
Bit0 SFR Address:
0xE2
Bits7–6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
PCA0ME: PCA Module I/0 Enable Bits
00: All PCA I/O unavailable at Port pins.
01: CEX0 routed to Port pin.
10: CEX0, CEX1 routed to Port pins.
11: CEX0, CEX1, CEX2 routed to Port pins.
CP0AOEN: Comparator0 Asynchronous Output Enable
0: Asynchronous CP0 unavailable at Port pin.
1: Asynchronous CP0 routed to Port pin.
CP0OEN: Comparator0 Output Enable
0: CP0 unavailable at Port pin.
1: CP0 routed to Port pin.
SYSCKE: /SYSCLK Output Enable
0: /SYSCLK unavailable at Port pin.
1: /SYSCLK output routed to Port pin.
SMB0OEN: SMBus I/O Enable
0: SMBus I/O unavailable at Port pins.
1: SDA, SCL routed to Port pins.
URX0EN: UART RX Enable
0: UART RX0 unavailable at Port pin.
1: UART RX0 routed to Port pin P0.5.
UTX0EN: UART TX Output Enable
0: UART TX0 unavailable at Port pin.
1: UART TX0 routed to Port pin P0.4.
Rev. 2.9
107