C8051F300_08 Datasheet, PDF (35/179 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F300/1/2/3/4/5
5. ADC0 (8-Bit ADC, C8051F300/2)
The ADC0 subsystem for the C8051F300/2 consists of two analog multiplexers (referred to collectively as
AMUX0) with 11 total input selections, a differential programmable gain amplifier (PGA), and a 500 ksps, 8-
bit successive-approximation-register ADC with integrated track-and-hold and programmable window
detector (see block diagram in Figure 5.1). The AMUX0, PGA, data conversion modes, and window detec-
tor are all configurable under software control via the Special Function Registers shown in Figure 5.1.
ADC0 operates in both Single-ended and Differential modes, and may be configured to measure any Port
pin, the Temperature Sensor output, or V_DD with respect to any Port pin or GND. The ADC0 subsystem is
enabled only when the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1. The ADC0 sub-
system is in low power shutdown when this bit is logic 0.
Temp
Sensor
AMUX0
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
VDD
10-to-1
AMUX
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
GND
9-to-1
AMUX
AMX0SL
ADC0CN
VDD
X
+
-
VDD
8-Bit
SAR
ADC
000
Start
Conversion 001
010
011
1xx
AD0BUSY (W)
Timer 0 Overflow
Timer 2 Overflow
Timer 1 Overflow
CNVSTR Input
8
ADC0CF
ADC0LT
ADC0GT
AD0WINT
Comb.
Logic
16
Figure 5.1. ADC0 Functional Block Diagram
Rev. 2.9
35