C8051F300_08 Datasheet, PDF (79/179 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F300/1/2/3/4/5
SFR Definition 8.11. IT01CF: INT0/INT1 Configuration
R/W
IN1PL
Bit7
R/W
IN1SL2
Bit6
R/W
IN1SL1
Bit5
R/W
IN1SL0
Bit4
R/W
IN0PL
Bit3
R/W
IN0SL2
Bit2
R/W
IN0SL1
Bit1
R/W
IN0SL0
Bit0
Reset Value
00000001
SFR Address:
0xE4
Note: Refer to SFR Definition 15.1 for INT0/1 edge- or level-sensitive interrupt selection.
Bit7:
Bits6–4:
IN1PL: /INT1 Polarity
0: /INT1 input is active low.
1: /INT1 input is active high.
IN1SL2–0: /INT1 Port Pin Selection Bits
These bits select which Port pin is assigned to /INT1. Note that this pin assignment is inde-
pendent of the Crossbar; /INT1 will monitor the assigned Port pin without disturbing the
peripheral that has been assigned the Port pin via the Crossbar. The Crossbar will not
assign the Port pin to a peripheral if it is configured to skip the selected pin (accomplished by
setting to ‘1’ the corresponding bit in register XBR0).
IN1SL2–0
000
001
010
011
100
101
110
111
/INT1 Port Pin
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
Bit3:
Bits2–0:
IN0PL: /INT0 Polarity
0: /INT0 interrupt is active low.
1: /INT0 interrupt is active high.
INT0SL2–0: /INT0 Port Pin Selection Bits
These bits select which Port pin is assigned to /INT0. Note that this pin assignment is inde-
pendent of the Crossbar. /INT0 will monitor the assigned Port pin without disturbing the
peripheral that has been assigned the Port pin via the Crossbar. The Crossbar will not
assign the Port pin to a peripheral if it is configured to skip the selected pin (accomplished by
setting to ‘1’ the corresponding bit in register XBR0).
IN0SL2–0
000
001
010
011
100
101
110
111
/INT0 Port Pin
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
Rev. 2.9
79