English
Language : 

C8051F300_08 Datasheet, PDF (164/179 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family
C8051F300/1/2/3/4/5
16.3. Watchdog Timer Mode
A programmable watchdog timer (WDT) function is available through the PCA Module 2. The WDT is used
to generate a reset if the time between writes to the WDT update register (PCA0CPH2) exceed a specified
limit. The WDT can be configured and enabled/disabled as needed by software.
With the WDTE bit set in the PCA0MD register, Module 2 operates as a watchdog timer (WDT). The Mod-
ule 2 high byte is compared to the PCA counter high byte; the Module 2 low byte holds the offset to be
used when WDT updates are performed. The Watchdog Timer is enabled on reset. Writes to some
PCA registers are restricted while the Watchdog Timer is enabled.
16.3.1. Watchdog Timer Operation
While the WDT is enabled:
• PCA counter is forced on.
• Writes to PCA0L and PCA0H are not allowed.
• PCA clock source bits (CPS2–CPS0) are frozen.
• PCA Idle control bit (CIDL) is frozen.
• Module 2 is forced into software timer mode.
• Writes to the module 2 mode register (PCA0CPM2) are disabled.
While the WDT is enabled, writes to the CR bit will not change the PCA counter state; the counter will run
until the WDT is disabled. The PCA counter run control (CR) will read zero if the WDT is enabled but user
software has not enabled the PCA counter. If a match occurs between PCA0CPH2 and PCA0H while the
WDT is enabled, a reset will be generated. To prevent a WDT reset, the WDT may be updated with a write
of any value to PCA0CPH2. Upon a PCA0CPH2 write, PCA0H plus the offset held in PCA0CPL2 is loaded
into PCA0CPH2 (See Figure 16.10).
PCA0MD
CWW
I DD
DT L
LEC
K
CCCE
PPPC
SSSF
210
PCA0CPH2
8-bit
Enable Comparator
Match
Reset
PCA0CPL2
8-bit Adder
PCA0H
PCA0L Overflow
Write to
PCA0CPH2
Adder
Enable
Figure 16.10. PCA Module 2 with Watchdog Timer Enabled
164
Rev. 2.9