C8051F300_08 Datasheet, PDF (132/179 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F300/1/2/3/4/5
14.1. Enhanced Baud Rate Generation
The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by
TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 14.2), which is not user
accessible. Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates.
The RX Timer runs when Timer 1 is enabled, and uses the same reload value (TH1). However, an
RX Timer reload is forced when a START condition is detected on the RX pin. This allows a receive to
begin any time a START is detected, independent of the TX Timer state.
Timer 1
TL1
Overflow
UART0
2
TX Clock
Start
Detected
TH1
RX Timer
Overflow
2
RX Clock
Figure 14.2. UART0 Baud Rate Logic
Timer 1 should be configured for Mode 2, 8-bit auto-reload (see Section “15.1.3. Mode 2: 8-bit Coun-
ter/Timer with Auto-Reload” on page 145). The Timer 1 reload value should be set so that overflows will
occur at two times the desired UART baud rate frequency. Note that Timer 1 may be clocked by one of five
sources: SYSCLK, SYSCLK / 4, SYSCLK / 12, SYSCLK / 48, or the external oscillator clock / 8. For any
given Timer 1 clock source, the UART0 baud rate is determined by Equation 14.1.
UartBaudRate
=
--------^T----1---^C---^L---^K---------
256 – T1H

1--
2
Equation 14.1. UART0 Baud Rate
Where T1_CLK is the frequency of the clock supplied to Timer 1, and T1H is the high byte of Timer 1 (reload
value). Timer 1 clock frequency is selected as described in Section “15.2. Timer 2” on page 151. A quick
reference for typical baud rates and system clock frequencies is given in Tables 14.1 through 14.6. Note
that the internal oscillator may still generate the system clock when the external oscillator is driving Timer 1
(see Section “15.1. Timer 0 and Timer 1” on page 143 for more details).
132
Rev. 2.9